| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | | | | | clk: meson: gxbb: mpll: use rw operation | Jerome Brunet | 2017-03-27 | 1 | -3/+3 | |
| | | * | | | | | clk: meson: mpll: add rw operation | Jerome Brunet | 2017-03-27 | 3 | -6/+180 | |
| | | * | | | | | clk: gxbb: put dividers and muxes in tables | Jerome Brunet | 2017-03-27 | 1 | -8/+20 | |
| | | * | | | | | clk: meson8b: put dividers and muxes in tables | Jerome Brunet | 2017-03-27 | 1 | -4/+18 | |
| | | * | | | | | clk: meson: add missing const qualifiers on gate arrays | Jerome Brunet | 2017-03-27 | 2 | -2/+2 | |
| | | * | | | | | clk: meson: fix SET_PARM macro | Jerome Brunet | 2017-03-27 | 1 | -1/+1 | |
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| | * | | | | | dt-bindings: clock: gxbb-clkc: Add GXL compatible variant | Neil Armstrong | 2017-04-04 | 1 | -1/+2 | |
| | * | | | | | clk: meson-gxbb: Expose GP0 dt-bindings clock id | Neil Armstrong | 2017-04-04 | 2 | -1/+2 | |
| | * | | | | | clk: meson-gxbb: Add MALI clock IDS | Neil Armstrong | 2017-04-04 | 2 | -1/+13 | |
| | * | | | | | dt-bindings: clk: gxbb: expose i2s output clock gates | Jerome Brunet | 2017-04-04 | 2 | -5/+10 | |
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| * | | | | | clk: aggregate return codes of notify chains | Peter De Schrijver | 2017-04-12 | 1 | -0/+2 | |
| * | | | | | clk: add clk_possible_parents debugfs file | Peter De Schrijver | 2017-04-12 | 1 | -0/+32 | |
| * | | | | | clk: imx: correct uart4_serial clock name in driver for i.MX6UL | Robin van der Gracht | 2017-04-12 | 1 | -1/+1 | |
| * | | | | | clk: zte: Mark pll config tables as const | Stephen Boyd | 2017-04-12 | 1 | -2/+2 | |
| * | | | | | clk: zte: add pll_vga clock for zx296718 | Shawn Guo | 2017-04-12 | 1 | -0/+24 | |
| * | | | | | clk: zte: pd_bit is not 0 on zx296718 | Shawn Guo | 2017-04-12 | 2 | -2/+16 | |
| * | | | | | clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks | Shawn Guo | 2017-04-12 | 1 | -3/+3 | |
| * | | | | | clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock | Robin van der Gracht | 2017-04-12 | 1 | -4/+5 | |
| * | | | | | Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/g... | Michael Turquette | 2017-04-12 | 20 | -268/+739 | |
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| | * | | | | | clk: tegra: Don't reset PLL-CX if it is already enabled | Jon Hunter | 2017-04-04 | 1 | -4/+4 | |
| | * | | | | | clk: tegra: Add missing Tegra210 clocks | Peter De Schrijver | 2017-04-04 | 4 | -8/+27 | |
| | * | | | | | clk: tegra: Propagate clk_out_x rate to parent | Alex Frid | 2017-04-04 | 1 | -2/+4 | |
| | * | | | | | clk: tegra: Fix build warnings on Tegra20/Tegra30 | Thierry Reding | 2017-03-20 | 2 | -2/+2 | |
| | * | | | | | clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on | Peter De Schrijver | 2017-03-20 | 1 | -0/+2 | |
| | * | | | | | clk: tegra: Add SATA seq input control | Peter De Schrijver | 2017-03-20 | 2 | -0/+26 | |
| | * | | | | | clk: tegra: Add Tegra210 special resets | Peter De Schrijver | 2017-03-20 | 2 | -0/+98 | |
| | * | | | | | clk: tegra: Rework pll_u | Peter De Schrijver | 2017-03-20 | 2 | -197/+272 | |
| | * | | | | | clk: tegra: Implement reset control reset | Mikko Perttunen | 2017-03-20 | 1 | -0/+16 | |
| | * | | | | | clk: tegra: Fix disable unused for clocks sharing enable bit | Peter De Schrijver | 2017-03-20 | 1 | -0/+3 | |
| | * | | | | | clk: tegra: Handle UTMIPLL IDDQ | Peter De Schrijver | 2017-03-20 | 2 | -0/+28 | |
| | * | | | | | clk: tegra: Add aclk | Peter De Schrijver | 2017-03-20 | 2 | -0/+12 | |
| | * | | | | | clk: tegra: Add super clock mux/divider | Peter De Schrijver | 2017-03-20 | 2 | -5/+89 | |
| | * | | | | | clk: tegra: Define Tegra210 DMIC clocks | Peter De Schrijver | 2017-03-20 | 3 | -1/+28 | |
| | * | | | | | clk: tegra: Fix constness for peripheral clocks | Peter De Schrijver | 2017-03-20 | 2 | -4/+4 | |
| | * | | | | | clk: tegra: Define Tegra210 DMIC sync clocks | Peter De Schrijver | 2017-03-20 | 4 | -25/+81 | |
| | * | | | | | clk: tegra: Add CEC clock | Peter De Schrijver | 2017-03-20 | 10 | -4/+10 | |
| | * | | | | | clk: tegra: Fix type for m field | Peter De Schrijver | 2017-03-20 | 1 | -1/+1 | |
| | * | | | | | clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation | Peter De Schrijver | 2017-03-20 | 1 | -1/+7 | |
| | * | | | | | clk: tegra: Don't warn for PLL defaults unnecessarily | Peter De Schrijver | 2017-03-20 | 1 | -6/+12 | |
| | * | | | | | clk: tegra: Remove non-existing pll_m_out1 clock | Peter De Schrijver | 2017-03-20 | 1 | -5/+0 | |
| | * | | | | | clk: tegra: Correct afi clock parent | Peter De Schrijver | 2017-03-20 | 1 | -1/+1 | |
| | * | | | | | clk: tegra: Fix ISP clock modelling | Peter De Schrijver | 2017-03-20 | 4 | -4/+13 | |
| | * | | | | | clk: tegra: Fix pll_a1 iddq register, add pll_a1 | Peter De Schrijver | 2017-03-20 | 1 | -1/+2 | |
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| * | | | | | cs-2000-cp: keep Reserved bit on each register | Kuninori Morimoto | 2017-04-12 | 1 | -3/+22 | |
| * | | | | | clk: qcom: msm8996: Fix the vfe1 powerdomain name | Rajendra Nayak | 2017-04-12 | 1 | -1/+1 | |
| * | | | | | clk: stm32f4: fix timeout management for pll and ready gate | Gabriel Fernandez | 2017-04-12 | 1 | -14/+29 | |
| * | | | | | clk: iproc: Remove redundant check | Ray Jui | 2017-04-12 | 1 | -1/+1 | |
| * | | | | | Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/... | Michael Turquette | 2017-04-12 | 12 | -255/+276 | |
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| | * | | | | | clk: rockchip: add pll_wait_lock for pll_enable | Elaine Zhang | 2017-03-22 | 1 | -0/+3 | |
| | * | | | | | clk: rockchip: rename RK1108 to RV1108 | Andy Yan | 2017-03-22 | 5 | -226/+226 | |
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