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* pinctrl: ti-iodelay: remove redundant unused variable devColin Ian King2017-11-081-4/+0
| | | | | | | | | | | | | The pointer dev is being assigned but is never used, hence it is redundant and can be removed. Cleans up clang warnings: drivers/pinctrl/ti/pinctrl-ti-iodelay.c:582:2: warning: Value stored to 'dev' is never read drivers/pinctrl/ti/pinctrl-ti-iodelay.c:701:2: warning: Value stored to 'dev' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: max77620: Use common error handling code in max77620_pinconf_set()Markus Elfring2017-11-081-10/+11
| | | | | | | | | | | | | | * Add a jump target so that a specific error message is stored only once at the end of this function implementation. * Replace two calls of the function "dev_err" by goto statements. * Adjust two condition checks. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: gemini: Implement clock skew/delay configLinus Walleij2017-11-082-6/+182
| | | | | | | | | This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: gemini: Use generic DT parserLinus Walleij2017-11-082-62/+5
| | | | | | | | We can just use the generic Device Tree parser code in this driver and save some code. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add skew-delay pin config and bindingsLinus Walleij2017-11-083-0/+11
| | | | | | | | | | | | | Some pin controllers (such as the Gemini) can control the expected clock skew and output delay on certain pins with a sub-nanosecond granularity. This is typically done by shunting in a number of double inverters in front of or behind the pin. Make it possible to configure this with a generic binding. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: armada-37xx: Add edge both type gpio irq supportKen Ma2017-10-311-0/+64
| | | | | | | | | | Current edge both type gpio irqs which need to swap polarity in each interrupt are not supported, this patch adds edge both type gpio irq support. Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: uniphier: remove eMMC hardware reset pin-muxMasahiro Yamada2017-10-313-6/+6
| | | | | | | | | | This is handled by the mmc-pwrseq-emmc driver, which controls an eMMC hardware reset via a GPIO line. Remove it from the function pin-mux settings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: Add iomux-route switching support for rk3288Heiko Stuebner2017-10-311-0/+20
| | | | | | | | | | | The rk3288 also has one function that can be routed to one of two pins, the hdmi cec functionality can use either gpio7c0 or gpio7c7. So add the route switching support for it. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Hans Verkuil <hans.verkuil@cisco.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Add Intel Cedar Fork PCH pin controller supportMika Westerberg2017-10-313-0/+384
| | | | | | | | | Intel Cedar Fork PCH is the successor of Intel Denverton PCH but it is based on the newer GPIO/pinctrl hardware block. Add a new pinctrl/GPIO driver to support it. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: intel: Make offset to interrupt status register configurableMika Westerberg2017-10-312-8/+15
| | | | | | | | | | | Some GPIO blocks have the interrupt status (GPI_IS) offset different than it normally is, so make it configurable. If no offset is specified we use the default. While there remove two unused constants from the core driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Enforce the strict mode by defaultMaxime Ripard2017-10-311-0/+1
| | | | | | | | | | | | The strict mode should always have been enabled on our driver, and leaving it unchecked just makes it harder to find a migration path as time passes. Let's enable it by default now so that hopefully the new SoCs should be safe. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Disable strict mode for old pinctrl driversMaxime Ripard2017-10-3111-2/+13
| | | | | | | | | | | | | | | Old pinctrl drivers will need to disable strict mode for various reasons, among which: - Some DT will still have a pinctrl group for each GPIO used, which will be rejected by pin_request. While we could remove those nodes, we still have to deal with old DTs. - Some GPIOs on these boards need to have their pin configuration changed (for bias or current), and there's no clear migration path Let's disable the strict mode on those SoCs so that there's no breakage. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Introduce the strict flagMaxime Ripard2017-10-312-1/+12
| | | | | | | | | | | | | | | | Our pinctrl device should have had strict set all along. However, it wasn't the case, and most of our old device trees also have a pinctrl group in addition to the GPIOs properties, which mean that we can't really turn it on now. All our new SoCs don't have that group, so we should still enable that mode on the newer one though. In order to enable it by default, add a flag that will allow to disable that mode that should be set by pinctrl drivers that cannot be migrated. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'sh-pfc-for-v4.15-tag2' of ↵Linus Walleij2017-10-2012-979/+2468
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.15 (take two) - Add Audio, HSCIF, I2C, and INTC-EX pin groups on R-Car H3 ES2.0, - Add Audio and PWM pin groups on R-Car D3, - Add support for RZ/A1M and RZ/A1L, - Add INTC-EX pin groups on R-Car M3-W, - Add SDHI voltage switching on RZ/G1E, - Make bias control and IOCTRL support more generic, - Add suspend/resume support for R-Car Gen3, - Small fixes and cleanups.
| * pinctrl: sh-pfc: Save/restore registers for PSCI system suspendGeert Uytterhoeven2017-10-202-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their pinctrl register state is lost. Note that as the boot loader skips most initialization after system resume, pinctrl register state differs from the state encountered during normal system boot, too. To fix this, save all GPIO and peripheral function select, module select, drive strength control, bias, and other I/O control registers during system suspend, and restore them during system resume. Note that to avoid overhead on platforms not needing it, the suspend/resume code has a build time dependency on sleep and PSCI support, and a runtime dependency on PSCI. Inspired by a patch in the BSP by Hien Dang. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Use generic IOCTRL register descriptionGeert Uytterhoeven2017-10-201-1/+11
| | | | | | | | | | | | | | Move R-Car M3-W I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Use generic IOCTRL register descriptionGeert Uytterhoeven2017-10-201-1/+11
| | | | | | | | | | | | | | | | Move R-Car H3 ES2.0 I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795-es1: Use generic IOCTRL register descriptionGeert Uytterhoeven2017-10-201-1/+11
| | | | | | | | | | | | | | | | Move R-Car H3 ES1.x I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: Add generic IOCTRL register descriptionGeert Uytterhoeven2017-10-201-0/+5
| | | | | | | | | | | | | | | | | | | | | | Add a generic way to describe IOCTRL registers (for e.g. SD I/O voltage and time delay control), like is already done for config, drive, and bias registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: Remove obsolete sh_pfc_pin_to_bias_info()Geert Uytterhoeven2017-10-203-24/+0
| | | | | | | | | | | | | | | | | | All users of sh_pfc_pin_to_bias_info() and the related data structures have been converted to sh_pfc_pin_to_bias_reg(), so those can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: r8a7778: Use generic bias register descriptionGeert Uytterhoeven2017-10-201-181/+222
| | | | | | | | | | | | | | | | | | | | Move R-Car M1A bias support over to the generic way to describe bias registers. As the new description is more compact, this decreases kernel size by ca. 148 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Use generic bias register descriptionGeert Uytterhoeven2017-10-201-241/+258
| | | | | | | | | | | | | | | | | | | | Move R-Car M3-W bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Use generic bias register descriptionGeert Uytterhoeven2017-10-201-241/+258
| | | | | | | | | | | | | | | | | | | | Move R-Car H3 ES2.0 bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 308 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795-es1: Use generic bias register descriptionGeert Uytterhoeven2017-10-201-241/+258
| | | | | | | | | | | | | | | | | | | | | | Move R-Car H3 ES1.x bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: Add sh_pfc_pin_to_bias_reg() helperGeert Uytterhoeven2017-10-202-0/+23
| | | | | | | | | | | | | | Add a helper to look up bias registers and bit number for a specific pin, using the generic bias register description. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: Add generic bias register descriptionGeert Uytterhoeven2017-10-201-0/+12
| | | | | | | | | | | | | | | | | | | | | | Add a generic way to describe bias registers (for pull-up/down control), like is already done for config and drive registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: Drop width parameter of sh_pfc_{read,write}_reg()Geert Uytterhoeven2017-10-206-31/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of sh_pfc_{read,write}_reg() already operate on 32-bit registers only. Hence make the 32-bit width implicit, and rename the functions to sh_pfc_{read,write}() to shorten lines. All accesses to 8-bit or 16-bit registers are still done using sh_pfc_{read,write}_raw_reg(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: Remove matching on plain sh-pfc platform deviceGeert Uytterhoeven2017-10-201-6/+1
| | | | | | | | | | | | | | | | | | | | As of commit 8682b3c522c639f3 ("sh-pfc: Remove platform device registration"), plain "sh-pfc" platform devices are no longer created. Hence remove their match entry, and the now obsolete checks for missing device IDs and driver data. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * pinctrl: sh-pfc: r8a7745: Implement voltage switching for SDHIBiju Das2017-10-161-0/+1
| | | | | | | | | | | | | | Voltage switching is the same as on the r8a7794. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77995: Remove USB0_IDIN and USB0_IDPU pinsGeert Uytterhoeven2017-10-161-4/+2
| | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017 removed the USB0_IDIN and USB0_IDPU pins on R-Car D3. This change has no functional impact, as these definitions were unused. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77995: Add Audio SSI pin supportKuninori Morimoto2017-10-111-0/+60
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77995: Add Audio clock pin supportKuninori Morimoto2017-10-111-0/+42
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Fix trivial typo in commentWolfram Sang2017-10-111-1/+1
| | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795-es1: Fix trivial typo in commentWolfram Sang2017-10-111-1/+1
| | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Fix trivial typo in commentWolfram Sang2017-10-111-1/+1
| | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functionsWolfram Sang2017-10-111-0/+283
| | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7796: Add support for INTC-EX IRQ pinsTakeshi Kihara2017-10-111-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most pins on the r8a7796 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". [takeshi.kihara.df: Ported from commit bb46f6f3f3bf ("pinctrl: sh-pfc: r8a7795: Add support for INTC-EX IRQ pins") to drivers/pinctrl/sh-pfc/pfc-r8a7796.c] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Add INTC-EX pins, groups and functionGeert Uytterhoeven2017-10-111-0/+60
| | | | | | | | | | | | | | | | | | Add pins, groups, and a function for the INTC-EX interrupt controller on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * dt-bindings: pinctrl: Add support for RZ/A1M and RZ/A1LChris Brandt2017-10-091-2/+4
| | | | | | | | | | | | | | Describe how to specify RZ/A1M and RZ/A1L devices. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: rza1: Add support for RZ/A1LChris Brandt2017-10-091-0/+134
| | | | | | | | | | | | | | | | | | Aspects like the number of ports and the location where peripherals are brought out differ between the RZ/A1H and RZ/A1L. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Restore sort orderGeert Uytterhoeven2017-10-051-16/+16
| | | | | | | | | | | | Move the SCIF_CLK pins where they belong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795-es1: Restore sort orderGeert Uytterhoeven2017-10-051-17/+17
| | | | | | | | | | | | Move the USB30 pins where they belong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Add I2C pin supportWolfram Sang2017-10-041-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since pinmuxing for I2C is equal on H3 ES1.0 and later versions, copy the I2C settings from ES1.0. Fixes this error in upstream for Salvator-XS: sh-pfc e6060000.pin-controller: function 'i2c2' not supported sh-pfc e6060000.pin-controller: invalid function i2c2 in map table i2c-rcar: probe of e6510000.i2c failed with error -22 Now, the bus works the same as with other Salvator boards. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a77995: Add PWM pins, groups and functionsTakeshi Kihara2017-10-041-0/+152
| | | | | | | | | | | | | | | | This patch adds support for PWM on r8a77995. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Add Audio SSI pin supportKuninori Morimoto2017-10-041-0/+231
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * pinctrl: sh-pfc: r8a7795: Add Audio clock pin supportKuninori Morimoto2017-10-041-0/+159
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | gpio: mcp23s08: add support for mcp23018Phil Reid2017-10-191-1/+14
| | | | | | | | | | | | | | | | | | This adds the required definitions for the mcp23018 which is the i2c variant of the mcp23s18. Signed-off-by: Phil Reid <preid@electromag.com.au> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | blackfin: Fix local <asm/gpio.h> includesLinus Walleij2017-10-195-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When making the pin control submenu globally visible, all kinds of oddities appear, in blackfin a few files were #including <linux/gpio.h> and relying on that to pull in <asm/gpio.h>. This was not working when pin control but not GPIOLIB was selected resulting in a breakage in allmodconfig. The code these files were using was still there and defined in <asm/gpio.h> just not pulle in from just including <linux/gpio.h> Simply add the required includes explicitly in the blackfin kernel core and everything compiles fine. Delete the use of the incorrect <linux/gpio.h> where possible. Add stubs to <asm/gpio.h> for the functions called from PM: these should probably also depend on !PINCTRL but since the global CONFIG_PM symbol is used to compile PM support, we need some more intrusive thing here, to be tested by Blackfin maintainers. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: adi2: Fix Kconfig build problemLinus Walleij2017-10-193-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The build robot is complaining on Blackfin: drivers/pinctrl/pinctrl-adi2.c: In function 'port_setup': >> drivers/pinctrl/pinctrl-adi2.c:221:21: error: dereferencing pointer to incomplete type 'struct gpio_port_t' writew(readw(&regs->port_fer) & ~BIT(offset), ^~ drivers/pinctrl/pinctrl-adi2.c: In function 'adi_gpio_ack_irq': >> drivers/pinctrl/pinctrl-adi2.c:266:18: error: dereferencing pointer to incomplete type 'struct bfin_pint_regs' if (readl(&regs->invert_set) & pintbit) ^~ It seems the driver need to include <asm/gpio.h> and <asm/irq.h> to compile. The Blackfin architecture was re-defining the Kconfig PINCTRL symbol which is not OK, so replaced this with PINCTRL_BLACKFIN_ADI2 which selects PINCTRL and PINCTRL_ADI2 just like most arches do. Further, the old GPIO driver symbol GPIO_ADI was possible to select at the same time as selecting PINCTRL. This was not working because the arch-local <asm/gpio.h> header contains an explicit #ifndef PINCTRL clause making compilation break if you combine them. The same is true for DEBUG_MMRS. Make sure the ADI2 pinctrl driver is not selected at the same time as the old GPIO implementation. (This should be converted to use gpiolib or pincontrol and move to drivers/...) Also make sure the old GPIO_ADI driver or DEBUG_MMRS is not selected at the same time as the new PINCTRL implementation, and only make PINCTRL_ADI2 selectable for the Blackfin families that actually have it. This way it is still possible to add e.g. I2C-based pin control expanders on the Blackfin. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | gpio: Cut old SX150X Kconfig optionLinus Walleij2017-10-171-9/+0
| | | | | | | | | | | | | | | | | | The SX150X driver was moved over to pin control a while back. The GPIO Kconfig symbol creates a circular dependency since it requires GPIOLIB and the pin control driver selects GPIOLIB so get rid of the old annoying Kconfig option. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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