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* drm: Add separate Kconfig option for fbdev helpersDaniel Vetter2013-10-1119-6/+31
* drm/i915: Fix VLV frame counter registersVille Syrjälä2013-10-111-8/+8
* drm/i915/vlv: add doc names to sideband fileJesse Barnes2013-10-111-1/+4
* drm/i915: don't save/restore CACHE_MODE_0 on gen7+Jesse Barnes2013-10-111-2/+5
* drm/i915: Fix pipe off timeout handling for pre-gen4Ville Syrjälä2013-10-111-15/+20
* drm/i915: increase the SWSCI DSLP default timeout to 50msPaulo Zanoni2013-10-111-1/+3
* drm/i915: Avoid tweaking RPS before it is enabledChris Wilson2013-10-102-10/+17
* drm/i915: tell the user KMS is required for gen6+Jani Nikula2013-10-101-1/+4
* drm/i915: Educate users in dmesg about reporting gpu hangsDaniel Vetter2013-10-101-2/+6
* drm/i915: Finish enabling rps before use by sysfs or debugfsTom O'Rourke2013-10-102-0/+22
* drm/i915: Capture the initial error-state when kicking stuck ringsChris Wilson2013-10-101-0/+2
* drm/i915: Rename primary_disabled to primary_enabledVille Syrjälä2013-10-104-11/+11
* drm/i915: Populate primary_disabled in intel_modeset_readout_hw_state()Ville Syrjälä2013-10-101-0/+1
* drm/i915: don't leak dp_connector at intel_ddi_initPaulo Zanoni2013-10-101-20/+42
* drm/i915/dp: update training set in a burst write with training pattern setJani Nikula2013-10-101-14/+14
* drm/i915: Do PCH and uncore init earlierBen Widawsky2013-10-101-4/+6
* drm/i915: wait for IPS_ENABLE when enabling IPSPaulo Zanoni2013-10-101-0/+8
* drm/i915: Keep intel_drv.h tidyDaniel Vetter2013-10-101-3/+2
* drm/i915: Remove gen specific checks in MMIOBen Widawsky2013-10-104-18/+12
* drm/i915: Create GEN specific write MMIOBen Widawsky2013-10-101-13/+74
* drm/i915: Create GEN specific read MMIOBen Widawsky2013-10-101-13/+59
* drm/i915: Extract common MMIO linesBen Widawsky2013-10-101-9/+21
* drm/i915: Create MMIO virtual functionsBen Widawsky2013-10-102-95/+104
* drm/i915: Move edram detection early_sanitizeBen Widawsky2013-10-102-10/+11
* drm/i915: Prevent using uninitialized MMIO funcsBen Widawsky2013-10-101-1/+1
* drm/i915: rip out gen2 reset codeDaniel Vetter2013-10-101-31/+0
* drm/i915: check that the i965g/gm 4G limit is really obeyedDaniel Vetter2013-10-101-0/+3
* drm/i915: Undo the PIPEA quirk for i845Chris Wilson2013-10-101-2/+1
* drm/i915: Use the real cpu max frequency for ring scalingBen Widawsky2013-10-101-6/+11
* drm/i915: Flush primary plane changes in sprite codeVille Syrjälä2013-10-101-0/+2
* drm/i915: WARN if primary plane state doesn't match expectationsVille Syrjälä2013-10-101-0/+4
* drm/i915: Rename intel_{enable, disable}_plane to intel_{enable, disable}_pri...Ville Syrjälä2013-10-101-13/+13
* drm/i915: Rename intel_flush_display_plane to intel_flush_primary_planeVille Syrjälä2013-10-104-12/+12
* drm/i915: Enable/disable IPS when primary is enabled/disabledVille Syrjälä2013-10-103-2/+23
* drm/i915: Do the fbc vs. primary plane enable/disable in the right orderVille Syrjälä2013-10-101-5/+6
* drm/i915: Save user requested plane coordinates only on successVille Syrjälä2013-10-101-9/+22
* drm/i915: Do a bit of cleanup in the sprite codeVille Syrjälä2013-10-101-9/+5
* drm/i915: Kill a goto from sprite disable codeVille Syrjälä2013-10-101-12/+9
* drm/i915: Reduce the time we hold struct mutex in sprite update_plane codeVille Syrjälä2013-10-101-11/+18
* drm/i915: Allow sprites to be configured on a disabled pipeVille Syrjälä2013-10-101-33/+32
* drm/i915: Set primary_disabled in intel_{enable, disable}_planeVille Syrjälä2013-10-101-0/+8
* drm/i915/dp: promote clock recovery failures to DRM_ERRORJani Nikula2013-10-101-2/+2
* drm/i915: Fix VGA_DISP_DISABLE checkVille Syrjälä2013-10-101-1/+1
* drm/i915: Use intel_PLL_is_valid() in vlv_find_best_dpll()Ville Syrjälä2013-10-101-11/+24
* drm/i915: Don't lie about findind suitable PLL settings on VLVVille Syrjälä2013-10-101-1/+4
* drm/i915: intel_limits_vlv_dac and intel_limits_vlv_hdmi are the sameVille Syrjälä2013-10-101-15/+2
* drm/i915: Remove unused dot_limit from VLV PLL limitsVille Syrjälä2013-10-101-4/+2
* drm/i915: Remove the unused p and m limits for VLVVille Syrjälä2013-10-101-4/+0
* drm/i915: Respect p2 divider minimum limit on VLVVille Syrjälä2013-10-101-3/+3
* drm/i915: Allow p1 divider 2 on VLVVille Syrjälä2013-10-101-1/+1
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