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* media: ccs: Add support for DDR OP SYS and OP PIX clocksSakari Ailus2020-12-071-1/+8
* media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus2020-12-072-20/+46
* media: ccs: Dual PLL supportSakari Ailus2020-12-072-3/+51
* media: ccs-pll: Add trivial dual PLL supportSakari Ailus2020-12-072-22/+196
* media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus2020-12-071-27/+37
* media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus2020-12-071-5/+7
* media: ccs-pll: Make VT divisors 16-bitSakari Ailus2020-12-071-26/+25
* media: ccs-pll: Rework bounds checksSakari Ailus2020-12-072-57/+95
* media: ccs-pll: Print relevant information on PLL treeSakari Ailus2020-12-071-19/+66
* media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus2020-12-071-23/+31
* media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus2020-12-073-29/+64
* media: ccs-pll: Split off VT subtree calculationSakari Ailus2020-12-071-124/+131
* media: ccs-pll: Add C-PHY supportSakari Ailus2020-12-071-9/+26
* media: ccs-pll: Add sanity checksSakari Ailus2020-12-071-0/+9
* media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus2020-12-073-8/+23
* media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus2020-12-073-6/+16
* media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus2020-12-073-1/+7
* media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus2020-12-074-19/+23
* media: ccs: Add support for lane speed modelSakari Ailus2020-12-071-1/+10
* media: ccs-pll: Add support for lane speed modelSakari Ailus2020-12-072-11/+31
* media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus2020-12-071-2/+2
* media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus2020-12-071-2/+1
* media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus2020-12-071-1/+1
* media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus2020-12-071-2/+9
* media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus2020-12-071-1/+1
* media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus2020-12-071-8/+4
* media: ccs-pll: Use the BIT macroSakari Ailus2020-12-071-2/+5
* media: ccs-pll: Document the structs in the header as well as the functionSakari Ailus2020-12-071-0/+89
* media: ccs-pll: Move the flags field down, away from 8-bit fieldsSakari Ailus2020-12-071-1/+1
* media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus2020-12-073-3/+4
* media: ccs-pll: Remove parallel bus supportSakari Ailus2020-12-072-15/+4
* media: ccs-pll: End search if there are no better values availableSakari Ailus2020-12-071-2/+8
* media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus2020-12-071-2/+2
* media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus2020-12-073-188/+209
* media: ccs-pll: Don't use div_u64 to divide a 32-bit numberSakari Ailus2020-12-071-1/+1
* media: dt-bindings: schema indentation fixesRob Herring2020-12-073-14/+14
* media: vivid: fix 'disconnect' error injectionHans Verkuil2020-12-073-30/+66
* media: rcar-vin: Mask VNCSI_IFMD registerJacopo Mondi2020-12-071-3/+22
* media: MAINTAINERS: Add myself as maintainer of the Amlogic GE2D driverNeil Armstrong2020-12-071-0/+9
* media: meson: Add M2M driver for the Amlogic GE2D Accelerator UnitNeil Armstrong2020-12-075-0/+1445
* media: dt-bindings: media: Add bindings for the Amlogic GE2D Accelerator UnitNeil Armstrong2020-12-071-0/+47
* media: cedrus: Make VP8 codec as capabilityJernej Skrabec2020-12-073-9/+20
* media: gspca: Fix memory leak in probeAlan Stern2020-12-071-0/+1
* media: doc: pixfmt-yuv: Move all planar YUV formats to common fileLaurent Pinchart2020-12-079-630/+487
* media: doc: pixfmt-yuv: Move all semi-planar YUV formats to common fileLaurent Pinchart2020-12-078-497/+464
* media: doc: pixfmt-yuv: Move all luma-only YUV formats to common fileLaurent Pinchart2020-12-0710-461/+127
* media: doc: pixfmt-packed-yuv: Clarify naming scheme for 4:4:4 formatsLaurent Pinchart2020-12-071-0/+14
* media: doc: pixfmt-packed-yuv: Express 4:4:4 formats in a more compact wayLaurent Pinchart2020-12-071-217/+56
* media: doc: pixfmt-packed-yuv: Fill padding bits with 'X'Laurent Pinchart2020-12-071-16/+16
* media: doc: pixfmt-yuv: Move all packed YUV formats to common fileLaurent Pinchart2020-12-077-388/+140
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