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* ARM: kprobes: Decode 32-bit Thumb table branch instructionsJon Medhurst2011-07-131-0/+25
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb load/store dual and load/store exclusive ↵Jon Medhurst2011-07-131-0/+56
| | | | | | | | | | | | instructions We reject probing of load/store exclusive instructions because any emulation routine could never succeed in gaining exclusive access as the exception framework clears the exclusivity monitor when a probes breakpoint is hit. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb load/store multiple instructionsJon Medhurst2011-07-131-0/+48
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Optimise emulation of LDM and STMJon Medhurst2011-07-131-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch improves the performance of LDM and STM instruction emulation. This is desirable because. - jprobes and kretprobes probe the first instruction in a function and, when the frame pointer is omitted, this instruction is often a STM used to push registers onto the stack. - The STM and LDM instructions are common in the body and tail of functions. - At the same time as being a common instruction form, they also have one of the slowest and most complicated simulation routines. The approach taken to optimisation is to use emulation rather than simulation, that is, a modified form of the instruction is run with an appropriate register context. Benchmarking on an OMAP3530 shows the optimised emulation is between 2 and 3 times faster than the simulation routines. On a Kirkwood based device the relative performance was very significantly better than this. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add common decoding function for LDM and STMJon Medhurst2011-07-133-51/+80
| | | | | | | | | | | | | | | | | The encoding of these instructions is substantially the same for both ARM and Thumb, so we can have common decoding and simulation functions. This patch moves the simulation functions from kprobes-arm.c to kprobes-common.c. It also adds a new simulation function (simulate_ldm1_pc) for the case where we load into PC because this may need to interwork. The instruction decoding is done by a custom function (kprobe_decode_ldmstm) rather than just relying on decoding table entries because we will later be adding optimisation code. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add load_write_pc()Jon Medhurst2011-07-132-0/+39
| | | | | | | | | This writes a value to PC which was obtained as the result of a LDR or LDM instruction. For ARMv5T and later this must perform interworking. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb hint instructionsJon Medhurst2011-07-131-1/+27
| | | | | | | | | | | | | | For hints which may have observable effects, like SEV (send event), we use kprobe_emulate_none which emulates the hint by executing the original instruction. For NOP we simulate the instruction using kprobe_simulate_nop, which does nothing. As probes execute with interrupts disabled this is also used for hints which may block for an indefinite time, like WFE (wait for event). Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Reject 16-bit Thumb SETEND, CPS and BKPT instructionsJon Medhurst2011-07-131-0/+4
| | | | | | | | | | | | | These are very rare and/or problematic to emulate so we will take the easy option and disallow probing them (as does the existing ARM implementation). Rejecting these instructions doesn't actually require any entries in the decoding table as it is the default case for instructions which aren't found. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb branch instructionsJon Medhurst2011-07-131-0/+38
| | | | | | | | | | | | | | | | We previously changed the behaviour of probes so that conditional instructions don't fire when the condition isn't met. For ARM branches, and Thumb branches in IT blocks, this means they don't fire if the branch isn't taken. For consistency, we implement the same for Thumb conditional branch instructions. This involves setting up insn_check_cc to point to the relevant condition checking function. As the emulation routine is only called when this condition passes, it doesn't need to check again and can unconditionally update PC. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Reject 16-bit Thumb SVC and UNDEFINED instructionsJon Medhurst2011-07-131-0/+8
| | | | | | | | SVC (SWI) instructions shouldn't occur in kernel code so we don't need to be able to probe them. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb IT instructionJon Medhurst2011-07-131-0/+33
| | | | | | | | | | The normal Thumb singlestepping routine updates the IT state after calling the instruction handler. We don't what this to happen after the IT instruction simulation sets the IT state, therefore we need to provide a custom singlestep routine. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb PUSH and POP instructionsJon Medhurst2011-07-131-0/+86
| | | | | | | | | | | | | | | | | | | These instructions are equivalent to stmdb sp!,{r0-r7,lr} ldmdb sp!,{r0-r7,pc} and we emulate them by transforming them into the 32-bit Thumb instructions stmdb r9!,{r0-r7,r8} ldmdb r9!,{r0-r7,r8} This is simpler, and almost certainly executes faster, than writing simulation functions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb CBZ and bit manipulation instructionsJon Medhurst2011-07-131-0/+29
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb PC- and SP-relative address instructionsJon Medhurst2011-07-131-0/+33
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb load and store instructionsJon Medhurst2011-07-131-0/+60
| | | | | | | | | | | Most of these instructions only operate on the low registers R0-R7 so they can make use of t16_emulate_loregs_rwflags. The instructions which use SP or PC for addressing have their own simulation functions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb special data instructionsJon Medhurst2011-07-131-0/+49
| | | | | | | | | | | These data-processing instructions operate on the full range of CPU registers, so to simulate them we have to modify the registers used by the instruction. We can't make use of the decoding table framework to do this because the registers aren't encoded cleanly in separate nibbles, therefore we need a custom decode function. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb BX and BLX instructionsJon Medhurst2011-07-131-0/+37
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add bx_write_pc()Jon Medhurst2011-07-131-0/+14
| | | | | | | | This writes a value to PC, with interworking. I.e. switches to Thumb or ARM mode depending on the state of the least significant bit. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb data-processing instructionsJon Medhurst2011-07-131-0/+81
| | | | | | | | | | | | | | These instructions only operate on the low registers R0-R7, therefore it is possible to emulate them by executing the original instruction unaltered if we restore and save these registers. This is what t16_emulate_loregs does. Some of these instructions don't update the PSR when they execute in an IT block, so there are two flavours of emulation functions: t16_emulate_loregs_{noit}rwflags Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: ptrace: Add APSR_MASK definition to ptrace.hJon Medhurst2011-07-131-1/+2
| | | | | | | | | APSR_MASK can be used to extract the APSR bits from the CPSR. The comment for these definitions is also changed because it was inaccurate as the existing defines didn't refer to any part of the APSR. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb hint instructionsJon Medhurst2011-07-133-1/+46
| | | | | | | | | | | | | | For hints which may have observable effects, like SEV (send event), we use kprobe_emulate_none which emulates the hint by executing the original instruction. For NOP we simulate the instruction using kprobe_simulate_nop, which does nothing. As probes execute with interrupts disabled this is also used for hints which may block for an indefinite time, like WFE (wait for event). Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Infrastructure for table driven decoding of CPU instructionsJon Medhurst2011-07-132-1/+505
| | | | | | | | | | | | | | | | | | | | | | | The existing ARM instruction decoding functions are a mass of if/else code. Rather than follow this pattern for Thumb instruction decoding this patch implements an infrastructure for a new table driven scheme. This has several advantages: - Reduces the kernel size by approx 2kB. (The ARM instruction decoding will eventually have -3.1kB code, +1.3kB data; with similar or better estimated savings for Thumb decoding.) - Allows programmatic checking of decoding consistency and test case coverage. - Provides more uniform source code and is therefore, arguably, clearer. For a detailed explanation of how decoding tables work see the in-source documentation in kprobes.h, and also for kprobe_decode_insn(). Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Extend arch_specific_insn to add pointer to emulated instructionJon Medhurst2011-07-132-0/+7
| | | | | | | | | | | | | | When we come to emulating Thumb instructions then, to interwork correctly, the code on in the instruction slot must be invoked with a function pointer which has the least significant bit set. Rather that set this by hand in every Thumb emulation function we will add a new field for this purpose to arch_specific_insn, called insn_fn. This also enables us to seamlessly share emulation functions between ARM and Thumb code. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add hooks to override singlestep()Jon Medhurst2011-07-134-9/+31
| | | | | | | | | | | | | | | | | | When a probe fires we must single-step the instruction which was replaced by a breakpoint. As the steps to do this vary between ARM and Thumb instructions we need a way to customise single-stepping. This is done by adding a new hook called insn_singlestep to arch_specific_insn which is initialised by the instruction decoding functions. These single-step hooks must update PC and call the instruction handler. For Thumb instructions an additional step of updating ITSTATE is needed. We do this after calling the handler because some handlers will need to test if they are running in an IT block. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Use conditional breakpoints for ARM probesJon Medhurst2011-07-132-3/+9
| | | | | | | | | | | | | Now we no longer trigger probes on conditional instructions when the condition is false, we can make use of conditional instructions as breakpoints in ARM code to avoid taking unnecessary exceptions. Note, we can't rely on not getting an exception when the condition check fails, as that is Implementation Defined on newer ARM architectures. We therefore still need to perform manual condition checks as well. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Don't trigger probes on conditional instructions when ↵Jon Medhurst2011-07-131-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | condition is false This patch changes the behavior of kprobes on ARM so that: Kprobes on conditional instructions don't trigger when the condition is false. For conditional branches, this means that they don't trigger in the branch not taken case. Rationale: When probes are placed onto conditionally executed instructions in a Thumb IT block, they may not fire if the condition is not met. This is because we use invalid instructions for breakpoints and "it is IMPLEMENTATION DEFINED whether the instruction executes as a NOP or causes an Undefined Instruction exception". Therefore, for consistency, we will ignore all probes on any conditional instructions when the condition is false. Alternative solutions seem to be too complex to implement or inconsistent. This issue was discussed on linux.arm.kernel in the thread titled "[RFC] kprobes with thumb2 conditional code" See http://comments.gmane.org/gmane.linux.linaro.devel/2985 Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add it_advance()Jon Medhurst2011-07-131-0/+25
| | | | | | | | This advances the ITSTATE bits in CPSR to their values for the next instruction. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add condition code checking to Thumb emulationJon Medhurst2011-07-131-0/+22
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add Thumb breakpoint supportJon Medhurst2011-07-132-14/+115
| | | | | | | | | | | | | | | | | Extend the breakpoint insertion and catching functions to support Thumb code. As breakpoints are no longer of a fixed size, the flush_insns macro is modified to take a size argument instead of an instruction count. Note, we need both 16- and 32-bit Thumb breakpoints, because if we were to use a 16-bit breakpoint to replace a 32-bit instruction which was in an IT block, and the condition check failed, then the breakpoint may not fire (it's unpredictable behaviour) and the CPU could then try and execute the second half of the 32-bit Thumb instruction. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: Kconfig: Allow kprobes on Thumb-2 kernelsJon Medhurst2011-07-131-1/+1
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add Thumb instruction decoding stubsJon Medhurst2011-07-134-2/+61
| | | | | | | | | Extend arch_prepare_kprobe to support probing of Thumb code. For the actual decoding of Thumb instructions, stub functions are added which currently just reject the probe. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Make kprobes framework work on Thumb-2 kernelsJon Medhurst2011-07-131-2/+35
| | | | | | | | Fix up kprobes framework so that it builds and correctly interworks on Thumb-2 kernels. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Make str_pc_offset a constant on ARMv7Jon Medhurst2011-07-132-0/+18
| | | | | | | | | | The str_pc_offset value is architecturally defined on ARMv7 onwards so we can make it a compile time constant. This means on Thumb kernels the runtime checking code isn't needed, which saves us from having to fix it to work for Thumb. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Move find_str_pc_offset into kprobes-common.cJon Medhurst2011-07-133-28/+35
| | | | | | | | Move str_pc_offset into kprobes-common.c as it will be needed by common code later. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Move is_writeback define to header file.Jon Medhurst2011-07-132-6/+6
| | | | | | | This will be used later in other files. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add kprobes-common.cJon Medhurst2011-07-134-92/+109
| | | | | | | | | | | | This file will contain the instruction decoding and emulation code which is common to both ARM and Thumb instruction sets. For now, we will just move over condition_checks from kprobes-arm.c This table is also renamed to kprobe_condition_checks to avoid polluting the public namespace with a too generic name. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Split out internal parts of kprobes.hJon Medhurst2011-07-134-17/+41
| | | | | | | | | | | | | | Later, we will be adding a considerable amount of internal implementation definitions to kprobe header files and it would be good to have these in local header file along side the source code, rather than pollute the existing header which is include by all users of kprobes. To this end, we add arch/arm/kernel/kprobes.h and move into this the existing internal defintions from arch/arm/include/asm/kprobes.h Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Rename kprobes-decode.c to kprobes-arm.cJon Medhurst2011-07-132-1/+2
| | | | | | | | | This file contains decoding and emulation functions for the ARM instruction set. As we will later be adding a file for Thumb and a file with common decoding functions, this renaming makes things clearer. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: Thumb-2: Support Thumb-2 in undefined instruction handlerJon Medhurst2011-07-133-26/+27
| | | | | | | | | | | | | | | | | This patch allows undef_hook's to be specified for 32-bit Thumb instructions and also to be used for thumb kernel-side code. 32-bit Thumb instructions are specified in the form: ((first_half << 16 ) | second_half) which matches the layout used by the ARM ARM. ptrace was handling 32-bit Thumb instructions by hooking the first halfword and manually checking the second half. This method would be broken by this patch so it is migrated to make use of the new Thumb-2 support. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: Thumb-2: Fix exception return sequence to restore stack correctlyJon Medhurst2011-07-131-7/+5
| | | | | | | | | | The implementation of svc_exit didn't take into account any stack hole created by svc_entry; as happens with the undef handler when kprobes are configured. The fix is to read the saved value of SP rather than trying to calculate it. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* Linux 3.0-rc7v3.0-rc7Linus Torvalds2011-07-121-1/+1
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* Documentation/Changes: remove some really obsolete textLinus Torvalds2011-07-121-25/+18
| | | | | | | | | | | | That file harkens back to the days of the big 2.4 -> 2.6 version jump, and was based even then on older versions. Some of it is just obsolete, and Jesper Juhl points out that it talks about kernel versions 2.6 and should be updated to 3.0. Remove some obsolete text, and re-phrase some other to not be 2.6-specific. Reported-by: Jesper Juhl <jj@chaosbits.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'v4l_for_linus' of ↵Linus Torvalds2011-07-129-139/+174
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6 * 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6: [media] msp3400: fill in v4l2_tuner based on vt->type field [media] tuner-core.c: don't change type field in g_tuner or g_frequency [media] cx18/ivtv: fix g_tuner support [media] tuner-core: power up tuner when called with s_power(1) [media] v4l2-ioctl.c: check for valid tuner type in S_HW_FREQ_SEEK [media] tuner-core: simplify the standard fixup [media] tuner-core/v4l2-subdev: document that the type field has to be filled in [media] v4l2-subdev.h: remove unused s_mode tuner op [media] feature-removal-schedule: change in how radio device nodes are handled [media] bttv: fix s_tuner for radio [media] pvrusb2: fix g/s_tuner support [media] v4l2-ioctl.c: prefill tuner type for g_frequency and g/s_tuner [media] tuner-core: fix tuner_resume: use t->mode instead of t->type [media] tuner-core: fix s_std and s_tuner
| * [media] msp3400: fill in v4l2_tuner based on vt->type fieldHans Verkuil2011-07-071-5/+7
| | | | | | | | | | | | | | | | The vt->type field determines how the msp3400 should fill in the tuner data, not whether the msp3400 is in radio mode or not. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
| * [media] tuner-core.c: don't change type field in g_tuner or g_frequencyHans Verkuil2011-07-071-19/+19
| | | | | | | | | | | | | | | | | | | | The tuner core should not silently change the type field in g_tuner and g_frequency. If the tuner is in a different mode than the one that was requested, then just fill in what you can and don't attempt to read afc, signal or rxsubchans values. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
| * [media] cx18/ivtv: fix g_tuner supportHans Verkuil2011-07-072-12/+4
| | | | | | | | | | | | | | | | The driver shouldn't override vt->type, and the tuner name should be based on vt->type as well. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
| * [media] tuner-core: power up tuner when called with s_power(1)Hans Verkuil2011-07-071-3/+7
| | | | | | | | | | | | | | | | | | | | | | Drivers must be able to rely on s_power to power up subdevices. Note that at this moment no driver attempts to power up tuners. This probably isn't surprising since s_power(1) was never implemented in tuner-core.c until now. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
| * [media] v4l2-ioctl.c: check for valid tuner type in S_HW_FREQ_SEEKHans Verkuil2011-07-071-3/+9
| | | | | | | | | | | | | | | | | | Prohibit attempts to change the tuner to a type that is different from the device node the ioctl is called from. I.e. the type must be RADIO for a radio node and ANALOG_TV for a video/vbi node. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
| * [media] tuner-core: simplify the standard fixupHans Verkuil2011-07-071-65/+28
| | | | | | | | | | | | | | | | Get rid of a number of unnecessary tuner_dbg messages by simplifying the std fixup function. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
| * [media] tuner-core/v4l2-subdev: document that the type field has to be filled inHans Verkuil2011-07-072-0/+36
| | | | | | | | | | | | | | | | | | | | The tuner ops g_frequency, g_tuner and s_tuner require that the tuner type field is filled in. Document this. The tuner-core doc is based on a patch from Mauro Carvalho Chehab <mchehab@redhat.com>. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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