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* spi: lpspi: Add i.MX8 boards support for lpspiClark Wang2019-03-181-11/+41
| | | | | | | Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-mem: stm32-qspi: add suspend/resume supportLudovic Barre2019-03-151-4/+35
| | | | | | | | This patch adds suspend and resume support for spi-stm32-qspi drivers. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge branch 'spi-5.1' into spi-5.2 for stm32Mark Brown2019-03-154-30/+26
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| * spi: spi-mem: stm32-qspi: avoid memory corruption at low frequencyLudovic Barre2019-03-151-3/+1
| | | | | | | | | | | | | | | | This patch solves a memory corruption seen at 8 MHz. To avoid such issue, timeout counter is disabled. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: rspi: Fix sequencer reset during initializationGeert Uytterhoeven2019-03-151-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | While the sequencer is reset after each SPI message since commit 880c6d114fd79a69 ("spi: rspi: Add support for Quad and Dual SPI Transfers on QSPI"), it was never reset for the first message, thus relying on reset state or bootloader settings. Fix this by initializing it explicitly during configuration. Fixes: 0b2182ddac4b8837 ("spi: add support for Renesas RSPI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: rspi: Fix register initialization while runtime-suspendedGeert Uytterhoeven2019-03-151-23/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Renesas RSPI/QSPI driver performs SPI controller register initialization in its spi_operations.setup() callback, without calling pm_runtime_get_sync() first, which may cause spurious failures. So far this went unnoticed, as this SPI controller is typically used with a single SPI NOR FLASH containing the boot loader: 1. If the device's module clock is still enabled (left enabled by the bootloader, and not yet disabled by the clk_disable_unused() late initcall), register initialization succeeds, 2. If the device's module clock is disabled, register writes don't seem to cause lock-ups or crashes. Data received in the first SPI message may be corrupted, though. Subsequent SPI messages seem to be OK. E.g. on r8a7791/koelsch, one bit is lost while receiving the 6th byte of the JEDEC ID for the s25fl512s FLASH, corrupting that byte and all later bytes. But until commit a2126b0a010905e5 ("mtd: spi-nor: refine Spansion S25FL512S ID"), the 6th byte was not considered for FLASH identification. Fix this by moving all initialization from the .setup() to the .prepare_message() callback. The latter is always called after the device has been runtime-resumed by the SPI core. This also makes the driver follow the rule that .setup() must not change global driver state or register values, as that might break a transfer in progress. Fixes: 490c97747d5dc77d ("spi: rspi: Add runtime PM support, using spi core auto_runtime_pm") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: imx: stop buffer overflow in RX FIFO flushTrent Piepho2019-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 71abd29057cb ("spi: imx: Add support for SPI Slave mode") added an RX FIFO flush before start of a transfer. In slave mode, the master may have sent more data than expected and this data will still be in the RX FIFO at the start of the next transfer, and so needs to be flushed. However, the code to do the flush was accidentally saving this data into the previous transfer's RX buffer, clobbering the contents of whatever followed that buffer. Change it to empty the FIFO and throw away the data. Every one of the RX functions for the different eCSPI versions and modes reads the RX FIFO data using the same readl() call, so just use that, rather than using the spi_imx->rx function pointer and making sure all the different rx functions have a working "throw away" mode. There is another issue, which affects master mode when switching from DMA to PIO. There can be extra data in the RX FIFO which triggers this flush code, causing memory corruption in the same manner. I don't know why this data is unexpectedly in the FIFO. It's likely there is a different bug or erratum responsible for that. But regardless of that, I think this is proper fix the for bug at hand here. Fixes: 71abd29057cb ("spi: imx: Add support for SPI Slave mode") Cc: Jiada Wang <jiada_wang@mentor.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: Fix zero length xfer bugChris Lesiak2019-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a bug for messages containing both zero length and unidirectional xfers. The function spi_map_msg will allocate dummy tx and/or rx buffers for use with unidirectional transfers when the hardware can only do a bidirectional transfer. That dummy buffer will be used in place of a NULL buffer even when the xfer length is 0. Then in the function __spi_map_msg, if he hardware can dma, the zero length xfer will have spi_map_buf called on the dummy buffer. Eventually, __sg_alloc_table is called and returns -EINVAL because nents == 0. This fix prevents the error by not using the dummy buffer when the xfer length is zero. Signed-off-by: Chris Lesiak <chris.lesiak@licor.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: fix SPI_BPW_RANGE_MASK() regressionArnd Bergmann2019-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Geert points out that I confused the min/max arguments that are reversed between SPI_BPW_RANGE_MASK() and GENMASK(). This time I have verified the result of the macro after fixing the arguments. Cc: Geert Uytterhoeven <geert@linux-m68k.org> Fixes: eefffb42f665 ("spi: work around clang bug in SPI_BPW_RANGE_MASK()") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: spi-fsl-qspi: use devm_spi_register_controllerVolker Haspel2019-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The driver does not clearly unregister the spi controller. Therefore calling an unbind and bind again will end up in a Kernel crash. The function devm_spi_register_controller will automatically be unregister the SPI device. Signed-off-by: Volker Haspel <volker.haspel@linutronix.de> Signed-off-by: John Ogness <john.ogness@linutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: imx: add module parameter to control DMA useTrent Piepho2019-03-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the boolean module parameter "use_dma" to control the use of DMA by the driver. There are about two dozen other drivers with a "use_dma" parameter of some sort. DMA may allow faster and more efficient transfers than using PIO, but it also adds overhead for small transfers. High speed receive operations may be less likely to have issues with FIFO overflow when using DMA than when using PIO. The eCSPI appears to insert a 4 bit pause after each word in DMA mode, not done in PIO mode, which can make DMA transfers 50% slower than PIO. In some cases DMA may be a net win while in others PIO might be. It depends on the application. So allow DMA to be enabled or disabled at the driver level. The default will be to have it enabled when possible. Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: work around clang bug in SPI_BPW_RANGE_MASK()Arnd Bergmann2019-03-111-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang-8 evaluates both sides of a ?: expression to check for valid arithmetic even in the side that is never taken. This results in a build warning: drivers/spi/spi-sh-msiof.c:1052:24: error: shift count >= width of type [-Werror,-Wshift-count-overflow] .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32), ^~~~~~~~~~~~~~~~~~~~~~~~~ Change the implementation to use the GENMASK() macro that does what we want here but does not have a problem with the shift count overflow. Link: https://bugs.llvm.org/show_bug.cgi?id=38789 Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mark Brown <broonie@kernel.org>
* | Merge branch 'spi-5.1' into spi-nextMark Brown2019-03-0466-2432/+5004
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| * spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3Geert Uytterhoeven2019-03-041-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | While the MSIOF variants in older SuperH and SH/R-Mobile SoCs support bits-per-word values in the full range 8..32, the variants present in R-Car Gen2 and Gen3 SoCs are restricted to 8, 16, 24, or 32. Obtain the value from family-specific sh_msiof_chipdata to fix this. Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: sifive: Remove redundant dev_err call in sifive_spi_probe()Wei Yongjun2019-02-221-1/+0
| | | | | | | | | | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: sifive: Remove spi_master_put in sifive_spi_remove()Wei Yongjun2019-02-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | The call to spi_master_put() in sifive_spi_remove() is redundant since the master is registered using devm_spi_register_master() and no reference hold by using spi_master_get() in sifive_spi_remove(). This is detected by Coccinelle semantic patch. Fixes: 484a9a68d669 ("spi: sifive: Add driver for the SiFive SPI controller") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * Merge branch 'for-5.0' of ↵Mark Brown2019-02-2010-74/+89
| |\ | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.1
| * | spi: sifive: Add driver for the SiFive SPI controllerYash Shah2019-02-193-0/+457
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for the SiFive SPI controller on the HiFive Unleashed board. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: sifive: Add DT documentation for SiFive SPI controllerYash Shah2019-02-191-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | DT documentation for SPI controller added. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: sprd: Add a prefix for SPI DMA channel macrosBaolin Wang2019-02-131-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add a prefix for SPI DMA channel macros to avoid namespace conflicts, and no functional changes. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: sprd: spi: sprd: Add DMA mode supportLanqing Liu2019-02-131-3/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add DMA mode support for the Spreadtrum SPI controller, and we will enable SPI interrupt to help to complete the SPI transfer work in DMA mode. Signed-off-by: Lanqing Liu <lanqing.liu@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | dt-bindings: spi: Add the DMA properties for the SPI dma modeLanqing Liu2019-02-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add the DMA properties for the SPI dma mode. Signed-off-by: Lanqing Liu <lanqing.liu@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: sprd: Add the SPI irq function for the SPI DMA modeLanqing Liu2019-02-131-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI irq event will use to complete the SPI work in the SPI DMA mode, so this patch is a preparation for the following DMA mode support. Moreover the SPI interrupt can be fired when removing the SPI controller, so we should make sure the SPI controller has stopped the queue in remove function before freeing the SPI irq. Signed-off-by: Lanqing Liu <lanqing.liu@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | dt-bindings: spi: imx: Add an entry for the i.MX8QM compatibleFabio Estevam2019-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add an entry for the "fsl,imx8mq-ecspi" compatible to describe the ECSPI version present on i.MX8M. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: use gpio[d]_set_value_cansleep for setting chipselect GPIOFelix Fietkau2019-02-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sleeping is safe inside spi_transfer_one_message, and some GPIO chips are running on slow busses (such as I2C GPIO expanders) and need to sleep for setting values. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: gpio: Advertise support for SPI_CS_HIGHJonathan Neuschäfer2019-02-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The spi-gpio driver already handles different chip select polarities, but so far this was not advertised in master->mode_bits. This patch fixes mmc_spi on top of spi_gpio, which is useful in some testing scenarios. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: sh-msiof: Replace spi_master by spi_controllerGeert Uytterhoeven2019-02-081-85/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: sh-hspi: Replace spi_master by spi_controllerGeert Uytterhoeven2019-02-081-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: rspi: Replace spi_master by spi_controllerGeert Uytterhoeven2019-02-081-85/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: add support for sam9x60 qspi controllerTudor Ambarus2019-02-061-35/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. It uses different transfer type bits in IFR register. It has dedicated registers to specify a read or a write instruction: Read Instruction Code Register (RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have identical fields. Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60Tudor Ambarus2019-02-061-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: add support for named peripheral clockTudor Ambarus2019-02-061-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Naming clocks is a good practice. Keep supporting unnamed peripheral clock, to be backward compatible with old DTs. While here, rename clk to pclk, to indicate that it is a peripheral clock. Suggested-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | dt-bindings: spi: atmel-quadspi: make "pclk" mandatoryTudor Ambarus2019-02-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Naming clocks is a good practice. Make "pclk" madatory even if we support unnamed clock in the driver, to be backward compatible with old DTs. Suggested-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | dt-bindings: spi: atmel-quadspi: update example to new clock bindingTudor Ambarus2019-02-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduced in: commit b60557876849 ("ARM: dts: at91: sama5d2: switch to new clock binding") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: rework transfer macrosTudor Ambarus2019-02-061-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the TFRTYP_TRSFR_ bitfields in 2: one bit encoding the mem/reg transfer type and one bit encoding the direction of the transfer (read/write). Remove NOP when setting read transfer type. Remove useless setting of write transfer type when op->data.dir == SPI_MEM_DATA_IN && !op->data.nbytes. QSPI_IFR_TFRTYP_TRSFR_WRITE is specific just to sama5d2 qspi, rename it to QSPI_IFR_SAMA5D2_WRITE_TRSFR. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: switch to SPDX license identifiersTudor Ambarus2019-02-061-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adopt the SPDX license identifiers to ease license compliance management. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: return appropriate error codeTudor Ambarus2019-02-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Return -ENOTSUPP when atmel_qspi_find_mode() fails. Propagate the error in atmel_qspi_exec_op(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: remove unnecessary castTudor Ambarus2019-02-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The cast is done implicitly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: fix naming schemeTudor Ambarus2019-02-061-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | Let general names to core drivers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: drop wrappers for iomem accessesTudor Ambarus2019-02-061-28/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | The wrappers hid that the accesses are relaxed. Drop them. Suggested-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: order header files inclusion alphabeticallyTudor Ambarus2019-02-061-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | Cosmetic change, no functional change. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: atmel-quadspi: cache MR value to avoid a write accessTudor Ambarus2019-02-061-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the controller by default in Serial Memory Mode (SMM) at probe. Cache Mode Register (MR) value to avoid write access when setting the controller in serial memory mode at exec_op(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: spi-fsl-dspi: Provide support for DSPI slave mode operation (Vybryd vf610)Lukasz Majewski2019-02-061-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NXP's Vybryd vf610 can work as a SPI slave device (the CS and clock signals are provided by master). It is possible to specify a single device to work in that mode. As we do use DMA for transferring data, the RX channel must be prepared for incoming data. Moreover, in slave mode we just set a subset of control fields in configuration registers (CTAR0, PUSHR). For testing the spidev_test program has been used. Test script for this patch can be found here: https://github.com/lmajewski/tests-spi/blob/master/tests/spi/spi_tests.sh Signed-off-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi-atmel: support inter-word delayJonas Bonn2019-01-311-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly. Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board). Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Mark Brown <broonie@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com> CC: Ludovic Desroches <ludovic.desroches@microchip.com> CC: linux-spi@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: support inter-word delay requirement for devicesJonas Bonn2019-01-312-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices are slow and cannot keep up with the SPI bus and therefore require a short delay between words of the SPI transfer. The example of this that I'm looking at is a SAMA5D2 with a minimum SPI clock of 400kHz talking to an AVR-based SPI slave. The AVR cannot put bytes on the bus fast enough to keep up with the SoC's SPI controller even at the lowest bus speed. This patch introduces the ability to specify a required inter-word delay for SPI devices. It is up to the controller driver to configure itself accordingly in order to introduce the requested delay. Note that, for spi_transfer, there is already a field word_delay that provides similar functionality. This field, however, is specified in clock cycles (and worse, SPI controller cycles, not SCK cycles); that makes this value dependent on the master clock instead of the device clock for which the delay is intended to provide some relief. This patch leaves this old word_delay in place and provides a time-based word_delay_us alongside it; the new field fits in the struct padding so struct size is constant. There is only one in-kernel user of the word_delay field and presumably that driver could be reworked to use the time-based value instead. The time-based delay is limited to 8 bits as these delays are intended to be short. The SAMA5D2 that I've tested this on limits delays to a maximum of ~100us, which is already many word-transfer periods even at the minimum transfer speed supported by the controller. Signed-off-by: Jonas Bonn <jonas@norrbonn.se> CC: Mark Brown <broonie@kernel.org> CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: linux-spi@vger.kernel.org CC: devicetree@vger.kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: mxs: add tracing to custom .transfer_one_message callbackUwe Kleine-König2019-01-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Driver specific implementations for .transfer_one_message need to call the tracing stuff themself. This is necessary to make spi tracing actually useful. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: spi-mem: spi-fsl-qspi: typo fix in author nameYogesh Narayan Gaur2019-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Typo fix in Author Boris Brezillon last name and update with new email address. Fixes: 84d043185dbe ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: spi-mem: spi-nxp-fspi: add module license infoYogesh Narayan Gaur2019-01-291-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MODULE_LICENSE info to fix below warning: WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o Typo fix in Boris Brezillon last name. Fixes: a5356aef6a90 ("spi: spi-mem: Add driver for NXP FlexSPI controller") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: pl022: add a message state STATE_TIMEOUT for timeout transferJiwei Sun2019-01-281-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When transfer timeout, give -EAGAIN to the message's status, and it can make the spi device driver choose repeated transimation or not. And if transfer timeout, output some useful information for tracing the issue. Signed-off-by: Jiwei Sun <jiwei.sun@windriver.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: Kconfig: imx: Update the help text to make it more genericFabio Estevam2019-01-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | The spi-imx driver supports both master and slave modes, so update the help text to make it more generic. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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