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* ARM: u300: only build for ARCH_MULTI_V5Arnd Bergmann2013-06-201-1/+1
| | | | | | | | This avoids impossible platform combinations, as we cannot build a combined V5 + V6/V7 kernel. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'imx-soc-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Arnd Bergmann2013-06-20280-2087/+4007
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc From Shawn Guo: imx soc changes for 3.11: * New SoCs i.MX6 Sololite and Vybrid VF610 support * imx5 and imx6 clock fixes and additions * Update clock driver to use of_clk_init() function * Refactor restart routine mxc_restart() to get it work for DT boot as well * Clean up mxc specific ulpi access ops * imx defconfig updates * tag 'imx-soc-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6: (29 commits) ARM: imx_v6_v7_defconfig: Enable Vybrid VF610 ARM: imx_v6_v7_defconfig: Enable imx-wm8962 by default ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresd ARM: imx_v6_v7_defconfig: Enable PWM and backlight options ARM: imx: Remove mxc specific ulpi access ops ARM: imx: add initial support for VF610 ARM: imx: add VF610 clock support ARM: imx_v6_v7_defconfig: enable parallel display ARM: imx: clk: No need to initialize phandle struct ARM: imx: irq-common: Include header to avoid sparse warning ARM: imx: Enable mx6 solo-lite support ARM: imx6: use common of_clk_init() call to initialize clocks ARM: imx6q: call of_clk_init() to register fixed rate clocks ARM: imx: imx_v6_v7_defconfig: Select CONFIG_DRM_IMX_TVE ARM: i.MX6: clk: add different DualLite MLB clock config ARM i.MX5: Add S/PDIF clocks ARM i.MX53: Add SATA clock ARM: imx6q: clk: add the eim_slow clock ARM: imx: remove MLB PLL from pllv3 ARM: imx: disable pll8_mlb in mx6q_clks ... Conflicts: arch/arm/Kconfig.debug (simple add/add conflict) Includes an update to 3.10-rc6 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: imx_v6_v7_defconfig: Enable Vybrid VF610Fabio Estevam2013-06-171-0/+1
| | | | | | | | | | | | | | Let VF610 SoC support be built by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx_v6_v7_defconfig: Enable imx-wm8962 by defaultNicolin Chen2013-06-171-0/+2
| | | | | | | | | | | | | | Enable imx-wm8962 and PM_RUNTIME, essential for WM8962 CODEC driver. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresdNicolin Chen2013-06-172-0/+44
| | | | | | | | | | | | | | WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx_v6_v7_defconfig: Enable PWM and backlight optionsFabio Estevam2013-06-171-0/+3
| | | | | | | | | | | | | | These options are useful for controlling backlight contrast via PWM. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: Remove mxc specific ulpi access opsMarkus Pargmann2013-06-175-141/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | There are ulpi access ops implemented in drivers/usb/phy/phy-ulpi.c. mxc access ops implement the same access operations within mach-imx. This patch removes the mxc ulpi file and uses phy-ulpi instead for imx_otg_ulpi_create. phy-ulpi successfully tested with i.MX27 Phytec phyCARD-S (pca100). Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: add initial support for VF610Jingchang Lu2013-06-173-0/+65
| | | | | | | | | | | | | | Add initial support for Freescale Vybrid VF610 SoC. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: add VF610 clock supportJingchang Lu2013-06-173-0/+508
| | | | | | | | | | | | | | | | | | Add clock support for Vybrid VF610. It uses dtc macro support to define all clock IDs in vf610-clock.h to keep clock IDs coherence between kernel and DT. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx_v6_v7_defconfig: enable parallel displayRogerio Pimentel2013-06-171-0/+2
| | | | | | | | | | | | | | | | Enable paralell display by default Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: clk: No need to initialize phandle structFabio Estevam2013-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | commit 84344b43c (ARM: i.MX5: Allow DT clock providers) introduce the following sparse warning: arch/arm/mach-imx/clk.c:12:43: warning: Using plain integer as NULL pointer There is no need to initialize phandle, so remove it. Cc: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: irq-common: Include header to avoid sparse warningFabio Estevam2013-06-171-0/+1
| | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/irq-common.c:24:5: warning: symbol 'mxc_set_irq_fiq' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: Enable mx6 solo-lite supportFabio Estevam2013-06-171-0/+1
| | | | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6: use common of_clk_init() call to initialize clocksShawn Guo2013-06-175-16/+10
| | | | | | | | | | | | | | | | Instead of explicitly calling clock initialization functions, we can declare the functions with CLK_OF_DECLARE() and then call common of_clk_init() to have them invoked properly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6q: call of_clk_init() to register fixed rate clocksShawn Guo2013-06-171-14/+5
| | | | | | | | | | | | | | As the fixed rate clocks are defined in device tree, we can just call of_clk_init() to register them. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: imx_v6_v7_defconfig: Select CONFIG_DRM_IMX_TVEFabio Estevam2013-06-171-0/+1
| | | | | | | | | | | | | | Let the mx53 TVE driver be built by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: i.MX6: clk: add different DualLite MLB clock configDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock configuration. Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM i.MX5: Add S/PDIF clocksPhilipp Zabel2013-06-172-1/+39
| | | | | | | | | | | | | | | | | | This patch adds the S/PDIF clocks for i.MX51 and i.MX53. Tested on i.MX53. The i.MX51 has a second set of spdif_root clock dividers, and on i.MX53 there is an additional input to the spdif_xtal mux. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM i.MX53: Add SATA clockSascha Hauer2013-06-172-1/+3
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6q: clk: add the eim_slow clockHuang Shijie2013-06-172-1/+3
| | | | | | | | | | | | | | Add the eim_slow clock, since the weim needs it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: remove MLB PLL from pllv3Jiada Wang2013-06-172-11/+0
| | | | | | | | | | | | | | | | | | MLB PLL should be handled internally in MLB driver, so remove it from pllv3. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: disable pll8_mlb in mx6q_clksJiada Wang2013-06-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | The MLB PLL clock's operation doesn't fit for clock framework and it should be handled internally in MLB driver. Remove initialization of pll8_mlb clock device but leave its declaration in mx6q_clks to avoid affecting imx6q clock numbering. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: add initial support for imx6slShawn Guo2013-06-174-0/+72
| | | | | | | | | | | | Add initial support for i.MX6 SoloLite. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: enable low-level debug support for imx6slShawn Guo2013-06-172-2/+21
| | | | | | | | | | | | | | Enable low-level debug support for i.MX6 SoloLite by adding the debug port definitions for the SoC. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: add clock support for imx6slShawn Guo2013-06-173-0/+428
| | | | | | | | | | | | | | | | | | Add clock support for i.MX6 SoloLite. It uses the dtc marco support to define all clock IDs in imx6sl-clock.h, which will be included by both clock driver and device tree sources, so that the data will stay sync all the time between kernel and DT. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: create mxc_arch_reset_init_dt() for DT bootShawn Guo2013-06-177-9/+26
| | | | | | | | | | | | | | | | | | | | The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to get clock. It's suitable for non-DT boot but not for DT boot where dynamic mapping and of_clk_get() should be used instead. Create mxc_arch_reset_init_dt() as the DT variant of mxc_arch_reset_init(), and change DT platforms to use it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: move clk_prepare() out from mxc_restart()Shawn Guo2013-06-1712-18/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's inappropriate to call clk_prepare() in mxc_restart(), because the restart routine could be called in atomic context. Move clk_get() and clk_prepare() into mxc_arch_reset_init() and only have the atomic part clk_enable() be called in mxc_restart(). As a result, mxc_arch_reset_init() needs to be called after clk gets initialized. While there, it also changes printk(KERN_ERR ...) to pr_err() and adds __init annotation for mxc_arch_reset_init(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: include <asm/io.h> in hardware.hShawn Guo2013-06-171-0/+1
| | | | | | | | | | | | | | As IOMEM is referenced in hardware.h, <asm/io.h> should be included there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: i.MX6: clk: add i.MX6 DualLite differencesDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and moves the gpu2_core configuration at that place. Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences by using cpu_is_mx6dl(). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: i.MX6: add i.MX6 specific L2 cache configurationDirk Behme2013-06-171-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To improve the performance and power consumption add an i.MX6 specific L2 cache initialization. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] with two additional improvements: a) The L2X0_POWER_CTRL has only the two bits we set. So no need to read the register before. Remove the register read done in Freescale's patch. b) In the L2X0_PREFETCH_CTRL register, besides the double linefill (bit[30]), additionally enable the instruction and data prefetch (bit[29-28]). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
| * ARM: i.MX5: Allow DT clock providersMartin Fuzzey2013-06-173-36/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently clock providers defined in the DT are not registered on i.MX5 platforms since of_clk_init() is not called. This is not a problem for the SOC's own clocks, which are registered in code, but prevents the DT being used to define clocks for external hardware. Fix this by calling of_clk_init() and actually using the DT to obtain the 4 SOC fixed clocks. These are already defined in the DT but were previously just used to manually obtain the rate. Fall back to the old scheme for non DT platforms. Since the same method may be useful for other i.MX platforms implement the imx_obtain_fixed_clock() function in common code. Actually changing other i.MX platforms to use this should be done later by someone with access to the appropriate hardware. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * Linux 3.10-rc6v3.10-rc6Linus Torvalds2013-06-151-1/+1
| |
| * Merge tag 'fixes-for-linus' of ↵Linus Torvalds2013-06-1513-29/+96
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "These are a little later than I planned on since I got caught up with handling merges for 3.11 most of the week. Another week, another batch of fixes for arm-soc platforms. Again, nothing controversial. A few more than would be ideal, but all are valid fixes. In particular the prima2 panic patch is critical since it fixes a problem where multiplatform kernels panic on all but prima2 hardware." * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled platforms ARM: prima2: fix incorrect panic usage arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe range ARM: Kirkwood: handle mv88f6282 cpu in __kirkwood_variant(). ARM: omap3: clock: fix wrong container_of in clock36xx.c ARM: dts: OMAP5: Fix missing PWM capability to timer nodes ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure line ARM: dts: AM33xx: Fix properties on gpmc node arm: omap2: fix AM33xx hwmod infos for UART2 ARM: OMAP3: Fix iva2_pwrdm settings for 3703
| | * Merge tag 'fixes-3.10-4' of git://git.infradead.org/users/jcooper/linux into ↵Olof Johansson2013-06-123-6/+9
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes From Jason Cooper, mvebu fixes for v3.10 round 4: - mvebu - fix PCIe ranges property so NOR flash is visible - kirkwood - fix identification of 88f6282 so MPPs can be set correctly * tag 'fixes-3.10-4' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe range ARM: Kirkwood: handle mv88f6282 cpu in __kirkwood_variant(). Signed-off-by: Olof Johansson <olof@lixom.net>
| | | * arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe rangeThomas Petazzoni2013-06-062-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | | * ARM: Kirkwood: handle mv88f6282 cpu in __kirkwood_variant().Nicolas Schichan2013-06-061-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPP_F6281_MASK would be previously be returned when on mv88f6282, which would disallow some valid MPP configurations. Commit 830f8b91 (arm: plat-orion: fix printing of "MPP config unavailable on this hardware") made this problem visible as an invalid MPP configuration is now correctly detected and not applied. Signed-off-by: Nicolas Schichan <nschichan@freebox.fr> Cc: <stable@vger.kernel.org> # v3.9.x Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * | ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled platformsTomasz Figa2013-06-111-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes legacy code on suspend/resume path being executed conditionally, on non-DT platforms only, to fix suspend/resume of DT-enabled systems, for which the code is inappropriate. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [olof: add #include <linux/of.h>] Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: prima2: fix incorrect panic usageHaojian Zhuang2013-06-112-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In prima2, some functions of checking DT is registered in initcall level. If it doesn't match the compatible name of sirf, kernel will panic. It blocks the usage of multiplatform on other verndor. The error message is in below. Knic - not syncing: unable to find compatible pwrc node in dtb CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc3-00006-gd7f26ea-dirty #86 [<c0013adc>] (unwind_backtrace+0x0/0xf8) from [<c0011430>] (show_stack+0x10/0x1) [<c0011430>] (show_stack+0x10/0x14) from [<c026f724>] (panic+0x90/0x1e8) [<c026f724>] (panic+0x90/0x1e8) from [<c03267fc>] (sirfsoc_of_pwrc_init+0x24/0x) [<c03267fc>] (sirfsoc_of_pwrc_init+0x24/0x58) from [<c0320864>] (do_one_initcal) [<c0320864>] (do_one_initcall+0x90/0x150) from [<c0320a20>] (kernel_init_freeab) [<c0320a20>] (kernel_init_freeable+0xfc/0x1c4) from [<c026b9e8>] (kernel_init+0) [<c026b9e8>] (kernel_init+0x8/0xe4) from [<c000e158>] (ret_from_fork+0x14/0x3c) Signen-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | Merge tag 'omap-for-v3.10/fixes-v3.10-rc4' of ↵Olof Johansson2013-06-097-14/+66
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes From Tony Lindgren, a set of small fixes for omaps for the -rc cycle: - am7303 iva2 reset PM regression fix - am33xx uart2 dma channel fix - am33xx gpmc properties fix - omap44xx rtc wake-up mux fix for nirq pins - omap36xx clock divider restore fix There's also one tiny non-critical .dts fix for omap5 timer pwm properties. * tag 'omap-for-v3.10/fixes-v3.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: omap3: clock: fix wrong container_of in clock36xx.c ARM: dts: OMAP5: Fix missing PWM capability to timer nodes ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure line ARM: dts: AM33xx: Fix properties on gpmc node arm: omap2: fix AM33xx hwmod infos for UART2 ARM: OMAP3: Fix iva2_pwrdm settings for 3703
| | | * \ Merge tag 'omap-fixes-b-for-3.10-rc' of ↵Tony Lindgren2013-06-082-10/+17
| | | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.10/fixes More OMAP hwmod and clock fixes for v3.10-rc. Fixes the AM33xx UART2. Also fixes some CCF-related breakage on OMAP36xx/37xx, affecting DSS at the very least. Basic test logs for this branch are here: http://www.pwsan.com/omap/testlogs/fixes_b_v3.10-rc/20130606093449/
| | | | * | ARM: omap3: clock: fix wrong container_of in clock36xx.cJean-Philippe Francois2013-06-061-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock have parent defined as clk_divider. Fix the function to use clk_divider. Tested with 3.9 on dm3730. Signed-off-by: Jean-Philippe François <jp.francois@cynove.com> Cc: NeilBrown <neilb@suse.de> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | | * | arm: omap2: fix AM33xx hwmod infos for UART2Thomas Petazzoni2013-06-031-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UART2 hwmod structure is pointing to the EDMA channels of UART1, which doesn't look right. This patch fixes this by making the UART2 hwmod structure to a new structure that lists the EDMA channels to be used by the UART2. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | Merge branch 'dts-fixes-for-3.10' of ↵Tony Lindgren2013-06-08206-1655/+4045
| | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt into omap-for-v3.10/fixes
| | | | * | | ARM: dts: OMAP5: Fix missing PWM capability to timer nodesSuman Anna2013-06-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM. The PWM capability property is missing from the node definitions of couple of timers. Add ti,timer-pwm attribute for timer 5, 6, 8 and 11. Signed-off-by: Suman Anna <s-anna@ti.com> [benoit.cousson@linaro.org: Update changelog and subject to highlight the fix] Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
| | | | * | | ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure lineKevin Hilman2013-06-032-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier commits ensured proper muxing of pins related to proper TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM: OMAP4: TWL: mux sys_drm_msecure as output for PMIC). However these only fixed legacy boot and not DT boot. For DT boot, the default mux values need to be set properly in DT. Special thanks to Nishanth Menon for the review and catching some major flaws in earlier versions. Tested on OMAP4430/Panda and OMAP4460/Panda-ES. Cc: Nishanth Menon <nm@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> [benoit.cousson@linaro.org: Slightly change the subject to align board name with file name] Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
| | | | * | | ARM: dts: AM33xx: Fix properties on gpmc nodeLars Poeschel2013-06-031-2/+2
| | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpmc driver is actually looking for "gpmc,num-cs" and "gpmc,num-waitpins" properties in DT. The binding doc also states this. Correct the properties in the dts to provide the right values for the gpmc driver. Signed-off-by: Lars Poeschel <poeschel@lemonage.de> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
| | | * | | ARM: OMAP3: Fix iva2_pwrdm settings for 3703Tony Lindgren2013-05-301-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a819c4f1 (ARM: OMAP3: PM: Only access IVA if one exists) changed PM to not access IVA registers on omaps that don't have them. Turns out we still need to idle iva2 as otherwise iva2_pwrdm will stay on and block deeper idle states. It seems that the only part of the reset that may not be needed is the setting of the iva2 boot mode to idle. But as that register seems to be there and is harmless if no iva2 is on the SoC, it's probably safest to do the complete reset. Acked-by: Mark A. Greer <mgreer@animalcreek.com> Acked-by: Kevin Hilman <khilman@linaro.org> Tested-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds2013-06-1520-81/+147
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull networking fixes from David Miller: 1) Fix RTNL locking in batman-adv, from Matthias Schiffer. 2) Don't allow non-passthrough macvlan devices to set NOPROMISC via netlink, otherwise we can end up with corrupted promisc counter values on the device. From Michael S Tsirkin. 3) Fix stmmac driver build with debugging defines enabled, from Dinh Nguyen. 4) Make sure name string we give in socket address in AF_PACKET is NULL terminated, from Daniel Borkmann. 5) Fix leaking of two uninitialized bytes of memory to userspace in l2tp, from Guillaume Nault. 6) Clear IPCB(skb) before tunneling otherwise we touch dangling IP options state and crash. From Saurabh Mohan. 7) Fix suspend/resume for davinci_mdio by using suspend_late and resume_early. From Mugunthan V N. 8) Don't tag ip_tunnel_init_net and ip_tunnel_delete_net with __net_{init,exit}, they can be called outside of those contexts. From Eric Dumazet. 9) Fix RX length error in sh_eth driver, from Yoshihiro Shimoda. 10) Fix missing sctp_outq initialization in some code paths of SCTP stack, from Neil Horman. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (21 commits) sctp: fully initialize sctp_outq in sctp_outq_init netiucv: Hold rtnl between name allocation and device registration. tulip: Properly check dma mapping result net: sh_eth: fix incorrect RX length error if R8A7740 ip_tunnel: remove __net_init/exit from exported functions drivers: net: davinci_mdio: restore mdio clk divider in mdio resume drivers: net: davinci_mdio: moving mdio resume earlier than cpsw ethernet driver net/ipv4: ip_vti clear skb cb before tunneling. tg3: Wait for boot code to finish after power on l2tp: Fix sendmsg() return value l2tp: Fix PPP header erasure and memory leak bonding: fix igmp_retrans type and two related races bonding: reset master mac on first enslave failure packet: packet_getname_spkt: make sure string is always 0-terminated net: ethernet: stmicro: stmmac: Fix compile error when STMMAC_XMIT_DEBUG used be2net: Fix 32-bit DMA Mask handling xen-netback: don't de-reference vif pointer after having called xenvif_put() macvlan: don't touch promisc without passthrough batman-adv: Don't handle address updates when bla is disabled batman-adv: forward late OGMs from best next hop ...
| | * | | | | sctp: fully initialize sctp_outq in sctp_outq_initNeil Horman2013-06-141-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 2f94aabd9f6c925d77aecb3ff020f1cc12ed8f86 (refactor sctp_outq_teardown to insure proper re-initalization) we modified sctp_outq_teardown to use sctp_outq_init to fully re-initalize the outq structure. Steve West recently asked me why I removed the q->error = 0 initalization from sctp_outq_teardown. I did so because I was operating under the impression that sctp_outq_init would properly initalize that value for us, but it doesn't. sctp_outq_init operates under the assumption that the outq struct is all 0's (as it is when called from sctp_association_init), but using it in __sctp_outq_teardown violates that assumption. We should do a memset in sctp_outq_init to ensure that the entire structure is in a known state there instead. Signed-off-by: Neil Horman <nhorman@tuxdriver.com> Reported-by: "West, Steve (NSN - US/Fort Worth)" <steve.west@nsn.com> CC: Vlad Yasevich <vyasevich@gmail.com> CC: netdev@vger.kernel.org CC: davem@davemloft.net Acked-by: Vlad Yasevich <vyasevich@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| | * | | | | netiucv: Hold rtnl between name allocation and device registration.Benjamin Poirier2013-06-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes a race condition between concurrent initializations of netiucv devices that try to use the same name. sysfs: cannot create duplicate filename '/devices/iucv/netiucv2' [...] Call Trace: ([<00000000002edea4>] sysfs_add_one+0xb0/0xdc) [<00000000002eecd4>] create_dir+0x80/0xfc [<00000000002eee38>] sysfs_create_dir+0xe8/0x118 [<00000000003835a8>] kobject_add_internal+0x120/0x2d0 [<00000000003839d6>] kobject_add+0x62/0x9c [<00000000003d9564>] device_add+0xcc/0x510 [<000003e00212c7b4>] netiucv_register_device+0xc0/0x1ec [netiucv] Signed-off-by: Benjamin Poirier <bpoirier@suse.de> Tested-by: Ursula Braun <braunu@de.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 13:12:19 +0100