summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* clk: renesas: cpg-mssr: Add early clock supportChris Brandt2018-09-262-21/+89
| | | | | | | | | Add support for SoCs that need to register core and module clocks early in order to use OF drivers that exclusively use macros such as TIMER_OF_DECLARE. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77970: Add TPU clockSergei Shtylyov2018-09-251-0/+1
| | | | | | | | | | | | The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke Matsushita, it was added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven2018-09-251-2/+2
| | | | | | | PLL0 runs at 4.8 GHz, i.e. EXTAL x 100. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0Fabrizio Castro2018-09-191-2/+4
| | | | | | | | | | This patch documents RZ/G2E (a.k.a. R8A774C0) bindings for the Clock Pulse Generator driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add r8a774c0 supportFabrizio Castro2018-09-195-0/+299
| | | | | | | | | | | | Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and Software Reset support. Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual: Hardware (Rev. 0.61, June 12, 2018)". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add r8a774c0 CPG Core Clock DefinitionsFabrizio Castro2018-09-191-0/+60
| | | | | | | | | | | | Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2g ("List of Clocks [RZ/G2E]") of the RZ/G2 Hardware User's Manual. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7743: Add r8a7744 supportBiju Das2018-09-193-2/+18
| | | | | | | | | | Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software Reset support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add r8a7744 CPG Core Clock DefinitionsBiju Das2018-09-191-0/+39
| | | | | | | | | | | Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's Manual. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 bindingBiju Das2018-09-191-5/+6
| | | | | | | | | | Add binding documentation for the RZ/G1N (R8A7744) Clock Pulse Generator driver. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* dt-bindings: clock: renesas: Convert to SPDX identifiersKuninori Morimoto2018-09-1915-93/+30
| | | | | | | | | This patch updates license to use SPDX-License-Identifier instead of verbose license text on Renesas related headers. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt2018-09-117-14/+300
| | | | | | | | | | | | | | | | Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module Standby. The Module Standby HW in the RZ/A series is very close to R-Car HW, except for how the registers are laid out. The MSTP registers are only 8-bits wide, there are no status registers (MSTPSR), and the register offsets are a little different. Since the RZ/A hardware manuals refer to these registers as the Standby Control Registers, we'll use that name to distinguish the RZ/A type from the R-Car type. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Rob Herring <robh@kernel.org> # DT bits Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77970: Add TMU clocksSergei Shtylyov2018-09-111-0/+5
| | | | | | | | | | | The TMU clocks weren't present in the original R8A77970 patch by Daisuke Matsushita, they were added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77970: Add CMT clocksSergei Shtylyov2018-09-111-0/+4
| | | | | | | | | | | Add the R8A77970 CMT module clocks. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy2018-09-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The clock for UARTs 0 through 2 is UART012, the clock for UARTs 3 through 7 is UART34567. For UART012, we stop the clock driver from changing the clock rate. This is because the Synopsys UART driver simply sets the reference clock to 16x the baud rate, but doesn't check if the actual rate is within the required tolerance. The RZ/N1 clock divider can't provide this (we have to rely on the UART's internal divider to set the correct clock rate), so you end up with a clock rate that is way off what you wanted. In addition, since the clock is shared between multiple UARTs, you don't want the driver trying to change the clock rate as it may affect the other UARTs (which may not have been configured yet, so you don't know what baud rate they will use). Normally, the clock rate is set early on before Linux to some very high rate that supports all of the clock rates you want. This change stops the UART34567 clock rate from changing for the same reasons. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHISergei Shtylyov2018-09-032-2/+67
| | | | | | | | | | | | | | On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2 SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver. We'll also need to support the SoC specific clock types, thus we're adding CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in the overridden cpg_clk_register() method; then, finally, add the SD-IF module clock (derived from the SD0 clock). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77980: Add CMT clocksSergei Shtylyov2018-09-031-0/+4
| | | | | | | | | | Now that RCLK has been added by Geert, we can add the CMT module clocks. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77990: Add missing I2C7 clockGeert Uytterhoeven2018-08-311-0/+1
| | | | | | | | | | | | | | | When trying to use I2C7 on R-Car E3: renesas-cpg-mssr e6150000.clock-controller: Cannot get module clock 1003: -2 i2c-rcar e6690000.i2c: failed to add to PM domain always-on: -2 i2c-rcar: probe of e6690000.i2c failed with error -2 Unlike other R-Car Gen3 SoCs, R-Car E3 has more than 7 I2C bus interfaces. Add the forgotten module clock for the 8th instance to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* clk: renesas: r8a77965: Add FDP clockHoan Nguyen An2018-08-281-0/+1
| | | | | | | | This patch adds FDP1-0 clock to the R8A77965 SoC. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add r8a774a1 supportBiju Das2018-08-276-4/+341
| | | | | | | | | | | | Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software Reset support. Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual: Hardware ((Rev. 0.61, June 12, 2018)". Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Add r8a774a1 CPG Core Clock DefinitionsBiju Das2018-08-271-0/+58
| | | | | | | | | | Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's Manual. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77965: Add SATA clockTakeshi Kihara2018-08-271-0/+1
| | | | | | | | | | This patch adds SATA clock to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [wsa: rebased to upstream base] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77980: Add RCLK for watchdog timerGeert Uytterhoeven2018-08-271-0/+4
| | | | | | | | On R-Car V3H, RCLK can be switched between EXTALR and the On-Chip Oscillator using mode pin MD19. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven2018-08-272-10/+13
| | | | | | | | | Make the existing support for selecting between clean and SSCG clocks using MD12 more generic, to allow using other mode pins for arbitrary clock selection. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a77995: Correct RCLK handlingGeert Uytterhoeven2018-08-271-2/+10
| | | | | | | | | | | | | | According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car D3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a77990: Correct RCLK handlingGeert Uytterhoeven2018-08-271-2/+10
| | | | | | | | | | | | | | According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Add support for RCKSEL clock selectionGeert Uytterhoeven2018-08-272-4/+26
| | | | | | | | Add a clock type and macro for defining clocks where the parent and divider are selected based on the value of the RCKCR.CKSEL bit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: cpg-mssr: Add support for fixed rate clocksGeert Uytterhoeven2018-08-272-0/+8
| | | | | | | | Add support for defining fixed rate clocks, to be used for on-chip oscillators. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a77980: Add OSC predivider configuration and clockGeert Uytterhoeven2018-08-271-11/+13
| | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC clock. Hence augment the configuration structure with all documented predivider values. Add the OSC clock using the configured predivider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a77965: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car M3-N does not have the CPG_RCKCR register. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car M3-N SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a7796: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR register was removed in R-Car M3-W ES1.1. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car M3-W SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a7795: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR register was removed in R-Car H3 ES2.0. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car H3 SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Add support for OSC EXTAL predividerGeert Uytterhoeven2018-08-272-0/+11
| | | | | | | | | | | | | | Add a clock type and macro for defining clocks using the OSC EXTAL predivider combined with a fixed divider. On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and thus must be specified in the configuration structure. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: rcar-gen3: Rename rint to .rGeert Uytterhoeven2018-08-273-3/+6
| | | | | | | | | | | All other internal clock names have a period prepended. Hence rename the internal RCLK from "rint" to ".r", and move it to the section where all other internal clocks are defined. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* Linux 4.19-rc1v4.19-rc1Linus Torvalds2018-08-261-2/+2
|
* Merge branch 'timers-urgent-for-linus' of ↵Linus Torvalds2018-08-261-0/+15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer update from Thomas Gleixner: "New defines for the compat time* types so they can be shared between 32bit and 64bit builds. Not used yet, but merging them now allows the actual conversions to be merged through different maintainer trees without dependencies We still have compat interfaces for 32bit on 64bit even with the new 2038 safe timespec/val variants because pointer size is different. And for the old style timespec/val interfaces we need yet another 'compat' interface for both 32bit native and 32bit on 64bit" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: y2038: Provide aliases for compat helpers
| * y2038: Provide aliases for compat helpersArnd Bergmann2018-08-221-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of the system call rework for 64-bit time_t, we are restructuring the way that compat syscalls deal with 32-bit time_t, reusing the implementation for 32-bit architectures. Christoph Hellwig suggested a rename of the associated types and interfaces to avoid the confusing usage of the 'compat' prefix for 32-bit architectures. To prepare for doing that in linux-4.20, add a set of macros that allows to convert subsystems separately to the new names and avoids some of the nastier merge conflicts. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Christoph Hellwig <hch@lst.de> Cc: y2038@lists.linaro.org Cc: John Stultz <john.stultz@linaro.org> Cc: Deepa Dinamani <deepa.kernel@gmail.com> Link: https://lkml.kernel.org/r/20180821203329.2089473-1-arnd@arndb.de
* | Merge branch 'ida-4.19' of git://git.infradead.org/users/willy/linux-daxLinus Torvalds2018-08-2628-679/+485
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull IDA updates from Matthew Wilcox: "A better IDA API: id = ida_alloc(ida, GFP_xxx); ida_free(ida, id); rather than the cumbersome ida_simple_get(), ida_simple_remove(). The new IDA API is similar to ida_simple_get() but better named. The internal restructuring of the IDA code removes the bitmap preallocation nonsense. I hope the net -200 lines of code is convincing" * 'ida-4.19' of git://git.infradead.org/users/willy/linux-dax: (29 commits) ida: Change ida_get_new_above to return the id ida: Remove old API test_ida: check_ida_destroy and check_ida_alloc test_ida: Convert check_ida_conv to new API test_ida: Move ida_check_max test_ida: Move ida_check_leaf idr-test: Convert ida_check_nomem to new API ida: Start new test_ida module target/iscsi: Allocate session IDs from an IDA iscsi target: fix session creation failure handling drm/vmwgfx: Convert to new IDA API dmaengine: Convert to new IDA API ppc: Convert vas ID allocation to new IDA API media: Convert entity ID allocation to new IDA API ppc: Convert mmu context allocation to new IDA API Convert net_namespace to new IDA API cb710: Convert to new IDA API rsxx: Convert to new IDA API osd: Convert to new IDA API sd: Convert to new IDA API ...
| * | ida: Change ida_get_new_above to return the idMatthew Wilcox2018-08-221-18/+12
| | | | | | | | | | | | | | | | | | | | | This calling convention makes more sense for the implementation as well as the callers. It even shaves 32 bytes off the compiled code size. Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | ida: Remove old APIMatthew Wilcox2018-08-223-67/+11
| | | | | | | | | | | | | | | | | | | | | | | | Delete ida_pre_get(), ida_get_new(), ida_get_new_above() and ida_remove() from the public API. Some of these functions still exist as internal helpers, but they should not be called by consumers. Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | test_ida: check_ida_destroy and check_ida_allocMatthew Wilcox2018-08-222-66/+58
| | | | | | | | | | | | | | | | | | | | | Move these tests from the userspace test-suite to the kernel test-suite. Also convert check_ida_random to the new API. Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | test_ida: Convert check_ida_conv to new APIMatthew Wilcox2018-08-222-46/+40
| | | | | | | | | | | | | | | | | | | | | | | | Move as much as possible to kernel space; leave the parts in user space that rely on checking memory allocation failures to detect the transition between an exceptional entry and a bitmap. Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | test_ida: Move ida_check_maxMatthew Wilcox2018-08-222-28/+23
| | | | | | | | | | | | | | | | | | Convert to new API and move to kernel space. Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | test_ida: Move ida_check_leafMatthew Wilcox2018-08-222-27/+25
| | | | | | | | | | | | | | | | | | | | | Convert to new API and move to kernel space. Take the opportunity to test the situation a little more thoroughly (ie at different offsets). Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | idr-test: Convert ida_check_nomem to new APIMatthew Wilcox2018-08-221-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | We can't move this test to kernel space because there's no way to force kmalloc to fail. But we can use the new API and check this works when the test is in userspace. Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | ida: Start new test_ida moduleMatthew Wilcox2018-08-227-7/+71
| | | | | | | | | | | | | | | | | | | | | Start transitioning the IDA tests into kernel space. Framework heavily cribbed from test_xarray.c. Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | target/iscsi: Allocate session IDs from an IDAMatthew Wilcox2018-08-223-30/+10
| | | | | | | | | | | | | | | | | | | | | Since the session is never looked up by ID, we can use the more space-efficient IDA instead of the IDR. Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | iscsi target: fix session creation failure handlingMike Christie2018-08-221-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem is that iscsi_login_zero_tsih_s1 sets conn->sess early in iscsi_login_set_conn_values. If the function fails later like when we alloc the idr it does kfree(sess) and leaves the conn->sess pointer set. iscsi_login_zero_tsih_s1 then returns -Exyz and we then call iscsi_target_login_sess_out and access the freed memory. This patch has iscsi_login_zero_tsih_s1 either completely setup the session or completely tear it down, so later in iscsi_target_login_sess_out we can just check for it being set to the connection. Cc: stable@vger.kernel.org Fixes: 0957627a9960 ("iscsi-target: Fix sess allocation leak in...") Signed-off-by: Mike Christie <mchristi@redhat.com> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Matthew Wilcox <willy@infradead.org>
| * | drm/vmwgfx: Convert to new IDA APIMatthew Wilcox2018-08-221-29/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Reorder allocation to avoid an awkward lock/unlock/lock sequence. Simpler code due to being able to use ida_alloc_max(), even if we can't eliminate the driver's spinlock. Signed-off-by: Matthew Wilcox <willy@infradead.org> Reviewed-by: Sinclair Yeh <syeh@vmware.com>
| * | dmaengine: Convert to new IDA APIMatthew Wilcox2018-08-221-16/+7
| | | | | | | | | | | | | | | | | | | | | Simpler and shorter code. Signed-off-by: Matthew Wilcox <willy@infradead.org> Acked-by: Vinod Koul <vkoul@kernel.org>
| * | ppc: Convert vas ID allocation to new IDA APIMatthew Wilcox2018-08-221-22/+4
| | | | | | | | | | | | | | | | | | | | | Removes a custom spinlock and simplifies the code. Also fix an error where we could allocate one ID too many. Signed-off-by: Matthew Wilcox <willy@infradead.org>