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* Merge patch series "riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION"Palmer Dabbelt2023-07-014-16/+12
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| * riscv: disable HAVE_LD_DEAD_CODE_DATA_ELIMINATION for LLDNick Desaulniers2023-06-261-1/+2
| * riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATIONZhangjin Wu2023-06-262-3/+4
| * vmlinux.lds.h: use correct .init.data.* section nameJisheng Zhang2023-06-261-1/+1
| * riscv: vmlinux-xip.lds.S: remove .alternative sectionJisheng Zhang2023-06-261-6/+0
| * riscv: move options to keep entries sortedJisheng Zhang2023-06-261-6/+6
* | RISC-V: Fix up some vector state related build failuresPalmer Dabbelt2023-07-011-0/+4
* | RISC-V: Document that V registers are clobbered on syscallsPalmer Dabbelt2023-07-011-0/+8
* | Merge tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-06-3078-251/+3077
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| * \ Merge patch series "dt-bindings: riscv: cpus: switch to unevaluatedProperties...Palmer Dabbelt2023-06-231-1/+7
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| | * | dt-bindings: riscv: cpus: switch to unevaluatedProperties: falseConor Dooley2023-06-221-1/+1
| | * | dt-bindings: riscv: cpus: add a ref the common cpu schemaConor Dooley2023-06-221-0/+6
| * | | riscv: hibernate: remove WARN_ON in save_processor_stateSong Shuai2023-06-231-1/+0
| * | | Merge patch series "riscv: Add independent irq/softirq stacks support"Palmer Dabbelt2023-06-235-13/+153
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| | * | | riscv: stack: Add config of thread stack sizeGuo Ren2023-06-222-11/+11
| | * | | riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACKGuo Ren2023-06-222-2/+39
| | * | | riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACKGuo Ren2023-06-225-2/+105
| * | | | Merge patch series "ISA string parser cleanups"Palmer Dabbelt2023-06-236-30/+123
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| | * | | | RISC-V: always report presence of extensions formerly part of the base ISAConor Dooley2023-06-213-0/+25
| | * | | | dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm supportConor Dooley2023-06-211-2/+2
| | * | | | RISC-V: remove decrement/increment dance in ISA string parserConor Dooley2023-06-211-8/+6
| | * | | | RISC-V: rework comments in ISA string parserConor Dooley2023-06-211-11/+59
| | * | | | RISC-V: validate riscv,isa at boot, not during ISA string parsingConor Dooley2023-06-212-9/+11
| | * | | | RISC-V: split early & late of_node to hartid mappingConor Dooley2023-06-213-2/+23
| | * | | | RISC-V: simplify register width check in ISA string parsingConor Dooley2023-06-211-8/+7
| * | | | | perf: RISC-V: Limit the number of counters returned from SBIViacheslav Mitrofanov2023-06-201-0/+6
| * | | | | riscv: replace deprecated scall with ecallFangrui Song2023-06-202-2/+2
| * | | | | riscv: uprobes: Restore thread.bad_causeTiezhu Yang2023-06-201-0/+2
| * | | | | riscv: mm: try VMA lock-based page fault handling firstJisheng Zhang2023-06-202-0/+34
| * | | | | riscv: mm: Pre-allocate PGD entries for vmalloc/modules areaBjörn Töpel2023-06-202-14/+60
| * | | | | Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"Palmer Dabbelt2023-06-197-16/+81
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| | * | | | | RISC-V: hwprobe: Expose Zba, Zbb, and ZbsEvan Green2023-06-193-7/+54
| | * | | | | RISC-V: Track ISA extensions per hartEvan Green2023-06-192-6/+22
| | * | | | | RISC-V: Add Zba, Zbs extension probingEvan Green2023-06-193-0/+6
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| * | | | | dt-bindings: riscv: cpus: drop unneeded quotesKrzysztof Kozlowski2023-06-191-3/+3
| * | | | | RISC-V/perf: Use standard interface to get INTC domainSunil V L2023-06-191-15/+2
| * | | | | RISC-V: ACPI : Fix for usage of pointers in different address spaceSunil V L2023-06-191-2/+2
| * | | | | riscv: hibernation: Remove duplicate call of suspend_restore_csrsSong Shuai2023-06-191-1/+0
| * | | | | riscv: hibernation: Replace jalr with jr before suspend_restore_regsSong Shuai2023-06-191-2/+2
| * | | | | riscv: mm: stub extable related functions/macros for !MMUJisheng Zhang2023-06-143-2/+11
| * | | | | riscv: say disabling zicbom if no or bad riscv,cbom-block-size foundBen Dooks2023-06-141-2/+2
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| * | | | Merge patch series "riscv: Add vector ISA support"Palmer Dabbelt2023-06-0845-51/+1805
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| | * | | selftests: add .gitignore file for RISC-V hwprobeAndy Chiu2023-06-081-0/+1
| | * | | selftests: Test RISC-V Vector prctl interfaceAndy Chiu2023-06-085-1/+318
| | * | | riscv: Add documentation for VectorAndy Chiu2023-06-082-0/+133
| | * | | riscv: Enable Vector code to be builtGuo Ren2023-06-082-1/+36
| | * | | riscv: detect assembler support for .option archAndy Chiu2023-06-081-1/+7
| | * | | riscv: Add sysctl to set the default vector rule for new processesAndy Chiu2023-06-081-1/+32
| | * | | riscv: Add prctl controls for userspace vector managementAndy Chiu2023-06-088-1/+162
| | * | | riscv: hwcap: change ELF_HWCAP to a functionAndy Chiu2023-06-083-1/+8
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