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* ARM: dts: uniphier: Add missing reg properties for glue layerKunihiko Hayashi2023-02-095-0/+14
| | | | | | | | | The nodes for glue layers should include "reg" property. Add the property according to the DT schema. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-3-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: uniphier: Align node names for SoC-dependent controller and PHYs ↵Kunihiko Hayashi2023-02-095-79/+79
| | | | | | | | | | | with bindings The node names for SoC-dependent controllers and PHYs should be generic ones according to the DT schemas. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-2-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'aspeed-6.3-devicetree' of ↵Arnd Bergmann2023-02-0911-3/+655
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt ASPEED device tree updates for 6.3 - New machines * Ufispace NCPLite AST2600 BMC * Facebook Greatlakes AST2600 BMC - Updates for ethanolx, bletchley and tyan s8036 * tag 'aspeed-6.3-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: dts: aspeed: p10bmc: Enable UART2 ARM: dts: aspeed: Add device tree for Ufispace NCPLite BMC dt-bindings: arm: aspeed: document Ufispace NCPLite BMC dt-bindings: vendor-prefixes: Add prefix for Ufi Space arm: dts: aspeed: tyan s8036: Enable kcs interrupts ARM: dts: aspeed: bletchley: Enable wdtrst1 ARM: dts: aspeed: bletchley: Rename flash1 label ARM: dts: aspeed: ethanolx: Add BIOS flash chip ARM: dts: aspeed: ethanolx: Enable CTS/RTS pins on UART1 ARM: dts: aspeed: ethanolx: Add label for the master partition ARM: dts: aspeed: ethanolx: Correct EEPROM device name ARM: dts: aspeed: ethanolx: Enable VUART ARM: dts: aspeed: greatlakes: Add Facebook greatlakes (AST2600) BMC dt-bindings: arm: aspeed: add Facebook Greatlakes board Link: https://lore.kernel.org/r/CACPK8XdbffU5yRSZF-zR2xv-+6aJK+hEXP8TOkW=SvS+nNTGxg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: dts: aspeed: p10bmc: Enable UART2Eddie James2023-02-013-0/+12
| | | | | | | | | | | | | | | | The APSS can be accessed over the second uart on these systems. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20230126220842.885965-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: Add device tree for Ufispace NCPLite BMCJordan Chang2023-01-272-0/+361
| | | | | | | | | | | | | | | | | | Add initial version of device tree for Ufispace NCPlite platform which is equipped with AST2600-based BMC. Signed-off-by: Jordan Chang <jordan.chang@ufispace.com> Link: https://lore.kernel.org/r/20230119102102.73414-4-jordan.chang@ufispace.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * dt-bindings: arm: aspeed: document Ufispace NCPLite BMCJordan Chang2023-01-271-0/+1
| | | | | | | | | | | | | | | | Document Ufispace NCPLite board compatible. Signed-off-by: Jordan Chang <jordan.chang@ufispace.com> Link: https://lore.kernel.org/r/20230119102102.73414-3-jordan.chang@ufispace.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * dt-bindings: vendor-prefixes: Add prefix for Ufi SpaceJordan Chang2023-01-271-0/+2
| | | | | | | | | | | | | | | | Add a vendor prefix for Ufi Space (https://www.ufispace.com). Signed-off-by: Jordan Chang <jordan.chang@ufispace.com> Link: https://lore.kernel.org/r/20230119102102.73414-2-jordan.chang@ufispace.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * arm: dts: aspeed: tyan s8036: Enable kcs interruptsAli El-Haj-Mahmoud2023-01-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the BIOS is built with kcs interrupts enabled, not enabling interrupts on the BMC results in very poor IPMI performance. The other way around (BIOS with interrupts disabled, BMC with interrupts enabled) doesn't suffer degraded IPMI performance. Enabling interrupts on the BMC covers both scenarios, and should be the default. TESTED: manually verified IPMI performance when BIOS is built with and without KCS interrupts. Signed-off-by: Ali El-Haj-Mahmoud <aaelhaj@google.com> Link: https://lore.kernel.org/r/20230118150030.2079226-1-aaelhaj@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: bletchley: Enable wdtrst1Potin Lai2023-01-231-0/+11
| | | | | | | | | | | | | | | | | | | | Enable WDTRST1 external signal to send a reset pulse to peripherals while BMC reset. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20221226054535.2836110-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: bletchley: Rename flash1 labelPotin Lai2023-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In OpenBMC phosphor-software-manager uses "alt-bmc" for the secondary flash label. Rename flash1 label to "alt-bmc" to support the dual image feature in OpenBMC. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20221226054535.2836110-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Add BIOS flash chipKonstantin Aladyshev2023-01-231-0/+11
| | | | | | | | | | | | | | | | | | Add a BIOS flash chip to the DTS to open a possibility to reflash the main CPU BIOS from the BMC. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111113934.1176-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Enable CTS/RTS pins on UART1Konstantin Aladyshev2023-01-231-1/+3
| | | | | | | | | | | | | | | | | | BMC UART1 is connected to the P0 CPU UART1. As the connection has CTS and RTS signals, enable these functions on the BMC side. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111115227.1357-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Add label for the master partitionKonstantin Aladyshev2023-01-231-0/+1
| | | | | | | | | | | | | | | | | | Add label "bmc" for the flash master partition. The master partition is required for the firmware update in the OpenBMC ecosystem. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111100105.707-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Correct EEPROM device nameKonstantin Aladyshev2023-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | BMC on the EthanolX board uses 24LC128 EEPROM chip for the configuration settings. The correct compatible string for this chip is "atmel,24c128". Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111113208.964-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Enable VUARTKonstantin Aladyshev2023-01-231-0/+7
| | | | | | | | | | | | | | | | | | | | Enable Virtual UART (VUART) module. This module provides virtual serial communication capabilities between host CPU and BMC and can be used for the Serial-Over-LAN (SoL) feature implementation. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111121917.1636-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: greatlakes: Add Facebook greatlakes (AST2600) BMCDelphine CC Chiu2023-01-232-0/+242
| | | | | | | | | | | | | | | | | | Add linux device tree entry related to greatlakes specific devices connected to BMC SoC. Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@Wiwynn.com> Link: https://lore.kernel.org/r/20221111034828.2377-3-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * dt-bindings: arm: aspeed: add Facebook Greatlakes boardDelphine CC Chiu2023-01-231-0/+1
| | | | | | | | | | | | | | | | | | Document the new compatibles used on Facebook Greatlakes Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@Wiwynn.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221111034828.2377-2-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* | Merge tag 'socfpga_dts_updates_for_v6.3' of ↵Arnd Bergmann2023-02-066-11/+64
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA dts updates for v6.3 - Align UART node with bindings - Add pinctrl properties for Stratix10/Agilex - Change address-cells to 2 to support 64-bit address for fpga region * tag 'socfpga_dts_updates_for_v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: socfpga: change address-cells to support 64-bit addressing arm64: dts: stratix10: add i2c pins for pinctrl arm64: dts: add pinctrl-single property for Stratix10/Agilex ARM: dts: socfpga: align UART node name with bindings Link: https://lore.kernel.org/r/20230206162425.311593-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | arm64: dts: socfpga: change address-cells to support 64-bit addressingDinh Nguyen2023-01-262-5/+4
| | | | | | | | | | | | | | | | | | | | | Update the address-cells and size-cells to 2 in order to support 64-bit addressing. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| * | arm64: dts: stratix10: add i2c pins for pinctrlDinh Nguyen2023-01-231-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the I2C pins definition to the Stratix10 devkit. This allows for the I2C driver to use pinctrl on the pins to allow for GPIO recovery. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: remove underscores in node names
| * | arm64: dts: add pinctrl-single property for Stratix10/AgilexDinh Nguyen2023-01-232-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Stratix10/Agilex has a pin control IP that can make use of the pinctrl-single driver. Add the pinctrl-single dts property for the Stratix10/Agilex platforms. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: no changes
| * | ARM: dts: socfpga: align UART node name with bindingsKrzysztof Kozlowski2023-01-233-6/+6
| |/ | | | | | | | | | | | | Bindings expect UART/serial node names to be "serial". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | Merge tag 'ti-k3-dt-for-v6.3' of ↵Arnd Bergmann2023-02-0628-35/+3688
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt TI K3 device tree updates for v6.3 New features: J784S4 SoC and EVM support AM68 and AM69 StarterKit, phyBOARD-Electra-AM642, Siemens IoT2050 M.2 AM62A7 SK additional peripherals AM62 SK USB support Non critical fixes AM62: McSPI Clock ID fixes MMC TAP value updates J7200: pinmux range update All: Cache DT node fixes Cleanups: Reorder dts Makefile entries alphabetically * tag 'ti-k3-dt-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (25 commits) arm64: dts: ti: Makefile: Rearrange entries alphabetically arch: arm64: dts: Add support for AM69 Starter Kit dt-bindings: arm: ti: Add binding for AM69 Starter Kit arm64: dts: ti: iot2050: Add support for M.2 variant dt-bindings: arm: ti: Add binding for Siemens IOT2050 M.2 variant arm64: dts: ti: iot2050: Add layout of OSPI flash arm64: dts: ti: k3-j7200: Fix wakeup pinmux range arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base board arm64: dts: ti: Add initial support for AM68 SK System on Module dt-bindings: arm: ti: Add binding for AM68 SK arm64: dts: Update cache properties for ti arm64: dts: ti: Add support for phyBOARD-Electra-AM642 dt-bindings: arm: ti: Add bindings for PHYTEC AM64x based hardware arm64: dts: ti: k3-am62a7-sk: Enable USB1 node arm64: dts: ti: k3-am62a7-sk: Enable ethernet port arm64: dts: ti: k3-am62a-main: Add more peripheral nodes arm64: dts: ti: k3-am62a-mcu: Add MCU domain peripherals arm64: dts: ti: Add support for J784S4 EVM board arm64: dts: ti: Add initial support for J784S4 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J784s4 ... Link: https://lore.kernel.org/r/642cf238-43e5-d6fa-68b5-a9dfbc0277bf@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | arm64: dts: ti: Makefile: Rearrange entries alphabeticallyVignesh Raghavendra2023-02-011-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Entries are first grouped as per SoC present on the board. Groups are sorted alphabetically. This makes it easy to know SoC to board mapping and also add new entries in alphabetical order. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230126071159.2337584-1-vigneshr@ti.com
| * | arch: arm64: dts: Add support for AM69 Starter KitDasnavis Sabiya2023-02-012-0/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM69 Starter Kit is a single board designed for TI AM69 SOC that provides advanced system integration in automotive ADAS applications, autonomous mobile robot and edge AI applications. The SOC comprises of Cortex-A72s in dual clusters, lockstep capable dual Cortex-R5F MCUs, Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Depth and Motion Processing Accelerators (DMPAC), Deep-learning Matrix Multiply Accelerator(MMA) and C7x floating point vector DSP AM69 SK supports the following interfaces: * 32 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x3 USB 3.0 Type-A ports * x1 USB 3.0 Type-C port * x1 UHS-1 capable micro-SD card slot * x4 MCAN instances * 32 GB eMMC Flash * 512 Mbit OSPI flash * x2 Display connectors * x1 PCIe M.2 M Key * x1 PCIe M.2 E Key * x1 4L PCIe Card Slot * x3 CSI2 Camera interface * 40-pin Raspberry Pi header Add initial support for the AM69 SK board. Design Files: https://www.ti.com/lit/zip/SPRR466 TRM: https://www.ti.com/lit/zip/spruj52 Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230119132958.124435-3-sabiya.d@ti.com
| * | dt-bindings: arm: ti: Add binding for AM69 Starter KitDasnavis Sabiya2023-02-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM69 Starter Kit is a single board designed for TI AM69 SoC. The AM69 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications, autonomous mobile robot and edge AI applications. Add DT binding for AM69 Starter Kit. Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230119132958.124435-2-sabiya.d@ti.com
| * | arm64: dts: ti: iot2050: Add support for M.2 variantchao zeng2023-01-262-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The M.2 variant comes with 2 slots, one B-keyed and another one E-keyed. They are configured by the firmware during startup. Also the device tree will be adjusted according to the detect or manually configured interface mode by the firmware. The kernel only carries a single configuration as base device tree. It has to be built with a symbols node so that the firmware can apply overlays for the connector modes. Signed-off-by: chao zeng <chao.zeng@siemens.com> [Jan: refactored to a single DT] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/878e3a023767b5a6d9d2cff09015678aaba13fce.1674110442.git.jan.kiszka@siemens.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | dt-bindings: arm: ti: Add binding for Siemens IOT2050 M.2 variantJan Kiszka2023-01-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new variant is derived from the Advanced PG2 board, replacing the MiniPCI slot with B and E-keyed M.2 slots. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/e49b4451b6c85ba28bdbbe42b25d9eeecebbe2d7.1674110442.git.jan.kiszka@siemens.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | arm64: dts: ti: iot2050: Add layout of OSPI flashJan Kiszka2023-01-261-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Describe the layout of the OSPI flash as the latest firmware uses it. Specifically the location of the U-Boot envs is important for userspace in order to access it. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/d135b246bd302060175276d3653f2891077eb109.1674110442.git.jan.kiszka@siemens.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | arm64: dts: ti: k3-j7200: Fix wakeup pinmux rangeVaishnav Achath2023-01-222-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The WKUP_PADCONFIG register region in J7200 has multiple non-addressable regions, split the existing wkup_pmx region as follows to avoid the non-addressable regions and include all valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230119042622.22310-1-vaishnav.a@ti.com
| * | arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base boardSinthu Raja2023-01-222-0/+337
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SK architecture comprises of baseboard and a SOM board. The AM68 Starter Kit's baseboard contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the base board. Therefore, add support for peripherals brought out in the base board. Schematics: https://www.ti.com/lit/zip/SPRR463 Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Tested-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230116071446.28867-4-sinthu.raja@ti.com
| * | arm64: dts: ti: Add initial support for AM68 SK System on ModuleSinthu Raja2023-01-221-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM68 Starter Kit (SK) is a low cost, small form factor board designed for TI’s AM68 SoC. TI’s AM68 SoC comprises of dual core A72, high performance vision accelerators, hardware accelerators, latest C71x DSP, high bandwidth real-time IPs for capture and display. The SoC is power optimized to provide best in class performance for industrial applications. AM68 SK supports the following interfaces: * 16 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 USB 3.1 Type-C port * x2 USB 3.1 Type-A ports * x1 PCIe M.2 M Key * 512 Mbit OSPI flash * x2 CSI2 Camera interface (RPi and TI Camera connector) * 40-pin Raspberry Pi GPIO header SK's System on Module (SoM) contains the SoC and DDR. Therefore, add DT node for the SOC and DDR on the SoM. Schematics: https://www.ti.com/lit/zip/SPRR463 TRM: http://www.ti.com/lit/pdf/spruj28 Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Tested-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230116071446.28867-3-sinthu.raja@ti.com
| * | dt-bindings: arm: ti: Add binding for AM68 SKSinthu Raja2023-01-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM68 Starter Kit is a low cost, small form factor board designed for TI's AM68 SoC which is optimized to provide best in class performance for industrial applications and add binding for the same. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230116071446.28867-2-sinthu.raja@ti.com
| * | arm64: dts: Update cache properties for tiPierre Gondois2023-01-167-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221107155825.1644604-24-pierre.gondois@arm.com
| * | arm64: dts: ti: Add support for phyBOARD-Electra-AM642Wadim Egorov2023-01-163-0/+509
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for phyCORE-AM64x SoM & phyBOARD-Electra-AM642 CB. The phyCORE-AM64x [1] is a SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family. A development Kit, called phyBOARD-Electra [2] is used as a carrier board reference design around the AM64x SoM. Supported features: * Debug UART * Heartbeat LED * GPIO buttons & LEDs * SPI NOR flash * eMMC * CAN * Ethernet * Micro SD card * I2C EEPROM * I2C RTC * I2C LED Dimmer * USB For more details, see: [1] Product page SoM: https://www.phytec.com/product/phycore-am64x [2] Product page CB: https://www.phytec.com/product/phyboard-am64x Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230104162927.1215033-2-w.egorov@phytec.de
| * | dt-bindings: arm: ti: Add bindings for PHYTEC AM64x based hardwareWadim Egorov2023-01-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add devicetree bindings for AM64x based phyCORE-AM64 SoM and phyBOARD-Electra RDK. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230104162927.1215033-1-w.egorov@phytec.de
| * | arm64: dts: ti: k3-am62a7-sk: Enable USB1 nodeVignesh Raghavendra2023-01-161-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable USB1 host port on AM62A7 SK. Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Acked-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-5-vigneshr@ti.com
| * | arm64: dts: ti: k3-am62a7-sk: Enable ethernet portVignesh Raghavendra2023-01-161-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | AM62A7 SK has a DP83867 PHY on the board connected to first port of CPSW, enable the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-4-vigneshr@ti.com
| * | arm64: dts: ti: k3-am62a-main: Add more peripheral nodesVignesh Raghavendra2023-01-161-0/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DT nodes for main domain SPI, PWM, DMA, CPSW (ethernet), mailbox, spinlock, USB and CAN. Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-3-vigneshr@ti.com
| * | arm64: dts: ti: k3-am62a-mcu: Add MCU domain peripheralsVignesh Raghavendra2023-01-161-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce DT nodes for MCU domain SPIs and GPIO modules. Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-2-vigneshr@ti.com
| * | arm64: dts: ti: Add support for J784S4 EVM boardApurva Nandan2023-01-162-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | J784S4 EVM board is designed for TI J784S4 SoC. It supports the following interfaces: * 32 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 Input Audio Jack, x1 Output Audio Jack * x1 USB2.0 Hub with two Type A host and x1 USB 3.1 Type-C Port * x2 4L PCIe connector * x1 UHS-1 capable micro-SD card slot * 512 Mbit OSPI flash, 1 Gbit Octal NAND flash, 512 Mbit QSPI flash, UFS flash. * x6 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * x2 ENET Expansion Connector, x1 GESI expander, x2 Display connector * x1 15-pin CSI header * x6 MCAN instances Add basic support for J784S4-EVM. Schematics: https://www.ti.com/lit/zip/sprr458 Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Tested-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112142725.77785-5-a-nandan@ti.com
| * | arm64: dts: ti: Add initial support for J784S4 SoCApurva Nandan2023-01-163-0/+1605
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The J784S4 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive, ADAS and industrial applications requiring AI at the network edge. This SoC extends the K3 Jacinto 7 family of SoCs with focus on raising performance and integration while providing interfaces, memory architecture and compute performance for multi-sensor, high concurrency applications. Some highlights of this SoC are: * Up to 8 Cortex-A72s, four clusters of lockstep capable dual Cortex-R5F MCUs, 4 C7x floating point vector DSPs with Matrix Multiply Accelerator (MMA) for deep learning and CNN. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Three CSI2.0 4L RX plus two CSI2.0 4L TX, two DSI Tx, one eDP/DP and one DPI interface. * Integrated gigabit ethernet switch, up to 8 ports (TDA4VH), two ports support 10Gb USXGMII; Two 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, Up to 20 MCANs, among other peripherals. See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022) for further details: http://www.ti.com/lit/zip/spruj52 Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112142725.77785-4-a-nandan@ti.com
| * | dt-bindings: pinctrl: k3: Introduce pinmux definitions for J784s4Apurva Nandan2023-01-151-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl macros for J784s4 SoC. These macro definitions are similar to that of J721s2, but adding new definitions to avoid any naming confusions in the soc dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112142725.77785-3-a-nandan@ti.com
| * | dt-bindings: arm: ti: Add bindings for J784s4 SoCApurva Nandan2023-01-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add binding for J784S4 SoC Signed-off-by: Apurva Nandan <a-nandan@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112142725.77785-2-a-nandan@ti.com
| * | arm64: dts: ti: k3-am625-sk: Add support for USBAswath Govindraju2023-01-151-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM62 SoC has two instances of USB and they are brought on to the board in the following way, -> USB0 instance - This is brought out to a USB TypeC connector on board through TPS6598 PD controller. The PD controller should decide the role based on CC pin in the connector. Unfortunately the irq line for the TPS isn't hooked up which is a mode not yet support by the driver (some patches were submitted earlier this year[0]). So for now the PD controller is left out and peripheral mode chosen. -> USB1 instance - This is brought out to a USB TypeA connector on board. Therefore, add the required device tree support for the above in the board dts file. 0: https://lore.kernel.org/lkml/f714ee55-ef47-317d-81b9-57020dda064b@ti.com/T/ Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112162847.973869-4-sjoerd@collabora.com
| * | arm64: dts: ti: k3-am62-main: Add support for USBAswath Govindraju2023-01-151-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM62 SoC has two instances of USB on it. Therefore, add support for the same. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112162847.973869-3-sjoerd@collabora.com
| * | arm64: dts: ti: k3-am62-main: Update OTAP and ITAP delay selectNitin Yadav2023-01-151-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UHS Class U1 sd-card are not getting detected due to incorrect OTAP/ITAP delay select values in linux. Update OTAP and ITAP delay select values for various speed modes. For sdhci0, update OTAP delay values for ddr52 & HS200 and add ITAP delay for legacy & mmc-hs. For sdhci1 & sdhci2, update OTAP & ITAP delay select recommended as in RIOT for various speed modes. Signed-off-by: Nitin Yadav <n-yadav@ti.com> [cherry-pick from vendor BSP] Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112162847.973869-2-sjoerd@collabora.com
| * | arm64: dts: ti: k3-am62-main: Fix clocks for McSPIDhruva Gole2023-01-151-3/+3
| |/ | | | | | | | | | | | | | | | | | | | | Fixes the clock Device ID's in the DT according to the tisci docs clock identifiers for AM62x Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Reviewed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103054840.1133711-1-d-gole@ti.com
* | Merge tag 'mvebu-dt64-6.3-1' of ↵Arnd Bergmann2023-02-038-8/+8
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt mvebu dt64 for 6.3 (part 1) Do not use anymore "marvell,armada3710" compatible string for the Armada 3720 boards. * tag 'mvebu-dt64-6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: marvell: Fix compatible strings for Armada 3720 boards Link: https://lore.kernel.org/r/87zg9w9j6l.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | arm64: dts: marvell: Fix compatible strings for Armada 3720 boardsPali Rohár2023-02-018-8/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | All Armada 3720 boards have Armada 3720 processor which is of Armada 3700 family and do not have Armada 3710 processor. So none of them should have compatible string for Armada 3710 processor. Fix compatible string for all these boards by removing wrong processor string "marvell,armada3710" and adding family string "marvell,armada3700" as the last one. (Note that this is same way how are defined Armada 3710 DTS files). [gclement: fix conflict for v6.2] Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-01 23:16:26 +0100