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* coresight: Do not default to CPU0 for missing CPU phandleSai Prakash Ranjan2019-07-044-10/+19
| | | | | | | | | | | | | | Coresight platform support assumes that a missing "cpu" phandle defaults to CPU0. This could be problematic and unnecessarily binds components to CPU0, where they may not be. In coresight etm and cpu-debug drivers, abort the probe for such cases. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/f1955ea19c714cf64ea54ec356a9aa85f3cd17b8.1562229018.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* dt-bindings: coresight: Change CPU phandle to required propertySai Prakash Ranjan2019-07-042-5/+7
| | | | | | | | | | | | | Do not assume the affinity to CPU0 if cpu phandle is omitted. Update the DT binding rules to reflect the same by changing it to a required property. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/0f7f4105d5ffea6ca4313271f3b3fee69da2106a.1562229018.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'misc-habanalabs-next-2019-07-04' of ↵Greg Kroah-Hartman2019-07-0422-463/+1249
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~gabbayo/linux into char-misc-next Oded writes: This tag contains the following changes for kernel 5.3: - Change the way the device's CPU access the host memory. This allows the driver to use the kernel API of setting DMA mask in a standard way (call it once). - Add a new debugfs entry to show the status of the internal DMA and compute engines. This is very helpful for debugging in case a command submission get stuck. - Return to the user a mask of the internal engines indicating their busy state. - Make sure to restore registers that can be modified by the user to their default values. Only applies to registers that are initialized by the driver. - Elimination of redundant and dead-code. - Support memset of the device's memory with size larger then 4GB - Force the user to set the device to debug mode before configuring the device's coresight infrastructure - Improve error printing in case of interrupts from the device * tag 'misc-habanalabs-next-2019-07-04' of git://people.freedesktop.org/~gabbayo/linux: (31 commits) habanalabs: Add busy engines bitmask to HW idle IOCTL habanalabs: Add debugfs node for engines status habanalabs: Update the device idle check habanalabs: Allow accessing host mapped addresses via debugfs habanalabs: add WARN in case of bad MMU mapping habanalabs: remove DMA mask hack for Goya habanalabs: set Goya CPU to use ASIC MMU habanalabs: add MMU mappings for Goya CPU habanalabs: initialize MMU context for driver habanalabs: de-couple MMU and VM module initialization habanalabs: initialize device CPU queues after MMU init docs/habanalabs: update text for some entries in sysfs habanalabs: add rate-limit to an error message habanalabs: remove simulator dedicated code habanalabs: restore unsecured registers default values habanalabs: clear sobs and monitors in context switch habanalabs: make tpc registers secured habanalabs: don't limit packet size for device CPU habanalabs: support device memory memset > 4GB habanalabs: print event name for fatal and non-RAZWI events ...
| * habanalabs: Add busy engines bitmask to HW idle IOCTLTomer Tayar2019-07-015-6/+43
| | | | | | | | | | | | | | | | | | | | | | The information which is currently provided as a response to the "HL_INFO_HW_IDLE" IOCTL is merely a general boolean value. This patch extends it and provides also a bitmask that indicates which of the device engines are busy. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: Add debugfs node for engines statusTomer Tayar2019-07-015-53/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Command submissions sent to the device are composed of command buffers which are targeted to different device engines, like DMA and compute entities. When a command submission gets stuck, knowing in which engine the stuck is, is crucial for debugging. This patch adds a debugfs node that exports this information, by displaying the engines' various registers that assemble their idle/busy status. The information retrieval is based on the is_device_idle ASIC function. The printout in this function, of the first detected busy engine, is removed because it becomes redundant in the presence of the more elaborated info of the new debugfs node. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: Update the device idle checkTomer Tayar2019-07-013-4/+425
| | | | | | | | | | | | | | | | | | | | | | | | The patch updates the device idle check: - Add reading the DMA core status register, because it is possible that a QMAN has finished its work but the DMA itself is still running. - Remove the MME shadow status check, as the MME ARCH status register includes the status of all MME shadows. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: Allow accessing host mapped addresses via debugfsTomer Tayar2019-06-163-19/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows using the addr/data32 debugfs nodes to access a device VA of a host mapped memory when the IOMMU is disabled. Due to the possible large amount of a user host mapped memory, the driver doesn't maintain a database with the host addresses per device VA. When the IOMMU is disabled, this missing info is being overcome by simply using phys_to_virt(). However, this is not useful when the IOMMU is enabled, and thus the enforced limitation. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: add WARN in case of bad MMU mappingOded Gabbay2019-05-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch checks if an MMU mapping is erroneous in that the physical address that is being mapped is NOT divisible by the page size. If that thing happens, then the H/W will issue a transaction which will be translated to a wrong address, because part of the address will not be taken (the remainder of address/page size). Because the physical address is being handled by the driver, a WARN is suitable here as it implies a bug in the driver code itself and not a user bug. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: remove DMA mask hack for GoyaOded Gabbay2019-05-291-15/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the non-standard DMA mask setting for Goya. Now that the device CPU goes through the MMU, we are not limited to allocating the CPU accessible memory area in the address space of under 39 bits. Therefore, we don't need to set the DMA masking twice during initialization, a practice that is not working on POWER architecture. The patch sets the DMA mask to 48 bits once during the initialization. The address of the CPU accessible memory area is configured to the MMU and the matching VA is given to the device CPU. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: set Goya CPU to use ASIC MMUOded Gabbay2019-05-291-3/+20
| | | | | | | | | | | | | | | | This patch configures the Goya CPU to actually go through the MMU for translation. The configuration is done after the configuration of the relevant MMU mappings. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: add MMU mappings for Goya CPUOded Gabbay2019-05-294-14/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary MMU mappings for the Goya CPU to access the device DRAM and the host memory. The first 256MB of the device DRAM is being mapped. That's where the F/W is running. The 2MB area located on the host memory for the purpose of communication between the driver and the device CPU is also being mapped. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: initialize MMU context for driverOded Gabbay2019-05-292-4/+13
| | | | | | | | | | | | | | This patch initializes the MMU structures for the kernel context. This is needed before we can configure mappings for the kernel context. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: de-couple MMU and VM module initializationOded Gabbay2019-05-293-20/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch initializes the MMU S/W structures before the VM S/W structures, instead of doing that as part of the VM S/W initialization. This is done because we need to configure some MMU mappings for the kernel context, before the VM is initialized. The VM initialization can't be moved earlier because it depends on the size of the DRAM, which is retrieved from the device CPU. Communication with the device CPU will require the MMU mappings to be configured and hence the de-coupling. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: initialize device CPU queues after MMU initOded Gabbay2019-05-293-48/+40
| | | | | | | | | | | | | | | | | | This patch changes the order of H/W IP initializations. The MMU needs to be initialized before the device CPU queues, because the CPU will go through the ASIC MMU in order to reach the host memory (where the queues are located). Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * docs/habanalabs: update text for some entries in sysfsOded Gabbay2019-06-061-18/+24
| | | | | | | | | | | | | | This patch updates the description of some entries in sysfs for the habanalabs driver. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: add rate-limit to an error messageOded Gabbay2019-06-061-1/+1
| | | | | | | | | | | | | | | | This patch changes the print of an error message about mis-configuration of the debug infrastructure to be rate-limited, to prevent flooding of kernel log, as these configuration requests can come at a high rate. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: remove simulator dedicated codeOded Gabbay2019-06-042-11/+0
| | | | | | | | | | | | | | | | | | | | This patch removes two code sections in the common code that contain code which is only relevant for simulator support (which is not upstreamed). This removal saves the need to update this code upstream, which is not needed anyway. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: restore unsecured registers default valuesDalit Ben Zoor2019-05-301-3/+16
| | | | | | | | | | | | | | | | | | unsecured registers can be changed by the user, and hence should be restored to their default values in context switch Signed-off-by: Dalit Ben Zoor <dbenzoor@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: clear sobs and monitors in context switchDalit Ben Zoor2019-05-301-0/+7
| | | | | | | | | | | | | | | | | | | | On context switch we need to ensure that each user is not be affected by other user, so we need to clear sync objects and monitors in context switch instead of in restore_phase_topology function. Signed-off-by: Dalit Ben Zoor <dbenzoor@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: make tpc registers securedDalit Ben Zoor2019-05-301-0/+16
| | | | | | | | | | | | | | | | | | Set protection bits for some tpc registers that should to be secured. Signed-off-by: Dalit Ben Zoor <dbenzoor@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: don't limit packet size for device CPUOded Gabbay2019-05-173-23/+3
| | | | | | | | | | | | | | | | | | | | | | This patch removes a limitation on the maximum packet size that is read by the device CPU as that limitation is not needed. Therefore, the patch also removes an elaborate calculation that is based on this limitation which is also not needed now. Instead, use a fixed value for the memory pool size of the packets. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: support device memory memset > 4GBOded Gabbay2019-05-161-19/+30
| | | | | | | | | | | | | | | | This patch adds support to the goya memset function to perform memset to device memory with size larger then 4GB. In this case, we need to use multiple LIN_DMA packets because a single packet supports up to 4GB. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: print event name for fatal and non-RAZWI eventsOmer Shpigelman2019-05-131-19/+98
| | | | | | | | | | | | | | | | This patch improves the error reporting in case of fatal and non-RAZWI events such that the event name is printed in addition to the IRQ number. Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: increase PCI ELBI timeout for PalladiumOmer Shpigelman2019-05-132-1/+11
| | | | | | | | | | | | | | | | This patch increases the timeout for PCI ELBI configuration to support low frequency Palladium images. Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: pass device pointer to asic-specific functionOded Gabbay2019-05-124-7/+8
| | | | | | | | | | | | | | | | | | | | This patch adds a new parameter that is passed to the add_end_of_cb_packets() asic-specific function. The parameter is the pointer to the driver's device structure. The function needs this pointer for future ASICs. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: change polling functions to macrosOded Gabbay2019-05-095-129/+81
| | | | | | | | | | | | | | | | | | | | | | This patch changes two polling functions to macros, in order to make their API the same as the standard readl_poll_timeout so we would be able to define the "condition for exit" when calling these macros. This will simplify the code as it will eliminate the need to check both for timeout and for the (cond) in the calling function. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: remove redundant memory clearOded Gabbay2019-05-091-2/+0
| | | | | | | | | | | | | | | | The driver allocates memory for fence object with GFP_ZERO flag, so there is no need to explicitly write 0 to the allocated object after the allocation. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: remove redundant CB size adjustmentOded Gabbay2019-05-091-8/+1
| | | | | | | | | | | | | | | | | | Driver-initiated DMA jobs are synchronized jobs, i.e. the driver polls on fence object until the job is finished. There is no interrupt from the device. Therefore, no need to add space for 2 * msg_prot packets to the end of the CB. Only a single msg_prot is needed (to write the fence). Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: check to load F/W before boot statusOded Gabbay2019-05-081-3/+3
| | | | | | | | | | | | | | | | This patch changes the order of checks when initializing the device CPU. We want first to check if we need to load the F/W, and only if we need to, then we want to check the status of the CPU boot program. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: remove dead code in habanalabs_drv.cOded Gabbay2019-05-081-30/+26
| | | | | | | | | | | | | | | | | | | | This patch removes some dead code that performs checks about variables with hard-coded values. The patch also moves the initialization of those variables to a separate function, that will possibly have different values per ASIC. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: force user to set device debug modeOded Gabbay2019-05-045-1/+73
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the implementation of the HL_DEBUG_OP_SET_MODE opcode in the DEBUG IOCTL. It forces the user who wants to debug the device to set the device into debug mode before he can configure the debug engines. The patch also makes sure to disable debug mode upon user releasing FD, in case the user forgot to disable debug mode. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: minor documentation and prints fixesOmer Shpigelman2019-05-052-4/+4
| | | | | | | | | | | | | | | | | | This patch fixes comments on various structure members and some spelling errors in log messages. Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: remove redundant CPU checksOmer Shpigelman2019-05-051-15/+5
| | | | | | | | | | | | | | | | | | | | This patch removes redundant CPU availability checks in: goya_test_queues() - will be done in goya_test_cpu_queue(). goya_ring_doorbell() - was done earlier in goya_send_cpu_message(). Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * habanalabs: improve a couple of error messagesOded Gabbay2019-05-042-3/+3
|/ | | | | | | | | | This patch improves the error message that is shown when a new user tries to open a new FD while there is already an existing user that is working on the device. It also improves the error message in case of missing firmware file. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
* ocxl: Allow contexts to be attached with a NULL mmAlastair D'Silva2019-07-033-7/+35
| | | | | | | | | | | | | | If an OpenCAPI context is to be used directly by a kernel driver, there may not be a suitable mm to use. The patch makes the mm parameter to ocxl_context_attach optional. Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Acked-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Frederic Barrat <fbarrat@linux.ibm.com> Acked-by: Nicholas Piggin <npiggin@gmail.com> Link: https://lore.kernel.org/r/20190620041203.12274-1-alastair@au1.ibm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* fsi: sbefifo: Don't fail operations when in SBE IPL stateEddie James2019-07-031-2/+2
| | | | | | | | | | | | SBE fifo operations should be allowed while the SBE is in any of the "IPL" states. Operations should succeed in this state. Fixes: 9f4a8a2d7f9d fsi/sbefifo: Add driver for the SBE FIFO Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/1561575415-3282-1-git-send-email-eajames@linux.ibm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: tmc: Smatch: Fix potential NULL pointer dereferenceSuzuki K Poulose2019-07-031-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the following report from Smatch, fix the potential NULL pointer dereference check. The patch 743256e214e8: "coresight: tmc: Clean up device specific data" from May 22, 2019, leads to the following Smatch complaint: drivers/hwtracing/coresight/coresight-tmc-etr.c:625 tmc_etr_free_flat_buf() warn: variable dereferenced before check 'flat_buf' (see line 623) drivers/hwtracing/coresight/coresight-tmc-etr.c 622 struct etr_flat_buf *flat_buf = etr_buf->private; 623 struct device *real_dev = flat_buf->dev->parent; ^^^^^^^^^^ The patch introduces a new NULL check 624 625 if (flat_buf && flat_buf->daddr) ^^^^^^^^ but the existing code assumed it can be NULL. 626 dma_free_coherent(real_dev, flat_buf->size, 627 flat_buf->vaddr, flat_buf->daddr); Cc: Dan Carpenter <dan.carpenter@oracle.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190621175205.24551-3-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: etm3x: Smatch: Fix potential NULL pointer dereferenceSuzuki K Poulose2019-07-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the following report from Smatch tool, make sure we have a valid drvdata before we dereference it to find the real dev. The patch 21d26b905c05: "coresight: etm: Clean up device specific data" from May 22, 2019, leads to the following Smatch complaint: ./drivers/hwtracing/coresight/coresight-etm3x.c:460 etm_get_trace_id() warn: variable dereferenced before check 'drvdata' (see line 458) ./drivers/hwtracing/coresight/coresight-etm3x.c 457 int trace_id = -1; 458 struct device *etm_dev = drvdata->csdev->dev.parent; ^^^^^^^^^ New dereference 459 460 if (!drvdata) ^^^^^^^^ Checked too late. Delete the check? 461 goto out; 462 Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190621175205.24551-2-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: Potential uninitialized variable in probe()Dan Carpenter2019-07-031-0/+1
| | | | | | | | | | | | | The "drvdata->atclk" clock is optional, but if it gets set to an error pointer then we're accidentally return an uninitialized variable instead of success. Fixes: 78e6427b4e7b ("coresight: funnel: Support static funnel") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: stable <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20190620221237.3536-6-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: etb10: Do not call smp_processor_id from preemptibleSuzuki K Poulose2019-07-031-4/+2
| | | | | | | | | | | | | | | | | | | | During a perf session we try to allocate buffers on the "node" associated with the CPU the event is bound to. If it is not bound to a CPU, we use the current CPU node, using smp_processor_id(). However this is unsafe in a pre-emptible context and could generate the splats as below : BUG: using smp_processor_id() in preemptible [00000000] code: perf/2544 Use NUMA_NO_NODE hint instead of using the current node for events not bound to CPUs. Fixes: 2997aa4063d97fdb39 ("coresight: etb10: implementing AUX API") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: stable <stable@vger.kernel.org> # 4.6+ Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190620221237.3536-5-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: tmc-etf: Do not call smp_processor_id from preemptibleSuzuki K Poulose2019-07-031-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During a perf session we try to allocate buffers on the "node" associated with the CPU the event is bound to. If it is not bound to a CPU, we use the current CPU node, using smp_processor_id(). However this is unsafe in a pre-emptible context and could generate the splats as below : BUG: using smp_processor_id() in preemptible [00000000] code: perf/2544 caller is tmc_alloc_etf_buffer+0x5c/0x60 CPU: 2 PID: 2544 Comm: perf Not tainted 5.1.0-rc6-147786-g116841e #344 Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Feb 1 2019 Call trace: dump_backtrace+0x0/0x150 show_stack+0x14/0x20 dump_stack+0x9c/0xc4 debug_smp_processor_id+0x10c/0x110 tmc_alloc_etf_buffer+0x5c/0x60 etm_setup_aux+0x1c4/0x230 rb_alloc_aux+0x1b8/0x2b8 perf_mmap+0x35c/0x478 mmap_region+0x34c/0x4f0 do_mmap+0x2d8/0x418 vm_mmap_pgoff+0xd0/0xf8 ksys_mmap_pgoff+0x88/0xf8 __arm64_sys_mmap+0x28/0x38 el0_svc_handler+0xd8/0x138 el0_svc+0x8/0xc Use NUMA_NO_NODE hint instead of using the current node for events not bound to CPUs. Fixes: 2e499bbc1a929ac ("coresight: tmc: implementing TMC-ETF AUX space API") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: stable <stable@vger.kernel.org> # 4.7+ Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190620221237.3536-4-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: tmc-etr: alloc_perf_buf: Do not call smp_processor_id from ↵Suzuki K Poulose2019-07-031-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | preemptible During a perf session we try to allocate buffers on the "node" associated with the CPU the event is bound to. If it is not bound to a CPU, we use the current CPU node, using smp_processor_id(). However this is unsafe in a pre-emptible context and could generate the splats as below : BUG: using smp_processor_id() in preemptible [00000000] code: perf/1743 caller is tmc_alloc_etr_buffer+0x1bc/0x1f0 CPU: 1 PID: 1743 Comm: perf Not tainted 5.1.0-rc6-147786-g116841e #344 Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Feb 1 2019 Call trace: dump_backtrace+0x0/0x150 show_stack+0x14/0x20 dump_stack+0x9c/0xc4 debug_smp_processor_id+0x10c/0x110 tmc_alloc_etr_buffer+0x1bc/0x1f0 etm_setup_aux+0x1c4/0x230 rb_alloc_aux+0x1b8/0x2b8 perf_mmap+0x35c/0x478 mmap_region+0x34c/0x4f0 do_mmap+0x2d8/0x418 vm_mmap_pgoff+0xd0/0xf8 ksys_mmap_pgoff+0x88/0xf8 __arm64_sys_mmap+0x28/0x38 el0_svc_handler+0xd8/0x138 el0_svc+0x8/0xc Use NUMA_NO_NODE hint instead of using the current node for events not bound to CPUs. Fixes: 22f429f19c4135d51e9 ("coresight: etm-perf: Add support for ETR backend") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: stable <stable@vger.kernel.org> # 4.20+ Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190620221237.3536-3-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: tmc-etr: Do not call smp_processor_id() from preemptibleSuzuki K Poulose2019-07-031-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During a perf session we try to allocate buffers on the "node" associated with the CPU the event is bound to. If it's not bound to a CPU, we use the current CPU node, using smp_processor_id(). However this is unsafe in a pre-emptible context and could generate the splats as below : BUG: using smp_processor_id() in preemptible [00000000] code: perf/1743 caller is alloc_etr_buf.isra.6+0x80/0xa0 CPU: 1 PID: 1743 Comm: perf Not tainted 5.1.0-rc6-147786-g116841e #344 Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Feb 1 2019 Call trace: dump_backtrace+0x0/0x150 show_stack+0x14/0x20 dump_stack+0x9c/0xc4 debug_smp_processor_id+0x10c/0x110 alloc_etr_buf.isra.6+0x80/0xa0 tmc_alloc_etr_buffer+0x12c/0x1f0 etm_setup_aux+0x1c4/0x230 rb_alloc_aux+0x1b8/0x2b8 perf_mmap+0x35c/0x478 mmap_region+0x34c/0x4f0 do_mmap+0x2d8/0x418 vm_mmap_pgoff+0xd0/0xf8 ksys_mmap_pgoff+0x88/0xf8 __arm64_sys_mmap+0x28/0x38 el0_svc_handler+0xd8/0x138 el0_svc+0x8/0xc Use NUMA_NO_NODE hint instead of using the current node for events not bound to CPUs. Fixes: 855ab61c16bf70b646 ("coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf()") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: stable <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20190620221237.3536-2-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* docs: misc-devices: convert files without extension to ReSTMauro Carvalho Chehab2019-07-039-42/+108
| | | | | | | | | Those files are also text files. Convert them to ReST and add to the misc-files index.rst. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Link: https://lore.kernel.org/r/b7dc829809673bd8cffe0e7bbe9c9308681c6fe2.1561756511.git.mchehab+samsung@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* fpga: dfl: fme: align PR buffer size per PR datawidthWu Hao2019-07-031-5/+9
| | | | | | | | | | | | | | | | | | | | | Current driver checks if input bitstream file size is aligned or not per PR data width (default 32bits). It requires one additional step for end user when they generate the bitstream file, padding extra zeros to bitstream file to align its size per PR data width, but they don't have to as hardware will drop extra padding bytes automatically. In order to simplify the user steps, this patch aligns PR buffer size per PR data width in driver, to allow user to pass unaligned size bitstream files to driver. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20190628004951.6202-4-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* fpga: dfl: fme: remove copy_to_user() in ioctl for PRWu Hao2019-07-031-3/+0
| | | | | | | | | | | | | | This patch removes copy_to_user() code in partial reconfiguration ioctl, as it's useless as user never needs to read the data structure after ioctl. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20190628004951.6202-3-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.Wu Hao2019-07-031-2/+2
| | | | | | | | | | | | | FME_PR_INTFC_ID is used as compat_id for fpga manager and region, but high 64 bits and low 64 bits of the compat_id are swapped by mistake. This patch fixes this problem by fixing register address. Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20190628004951.6202-2-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: msu: Start read iterator from a non-empty windowAlexander Shishkin2019-07-031-9/+33
| | | | | | | | | | | | | | | | In multi-window mode, the read iterator is supposed to start from the window with the oldest data, which is, chronologically, the next window after the one with the newest data. This, however, fails to take into account the potentially empty windows, so in short trace sessions it's possible to have a lot of zeroes read from the character device first. Fix this by skipping over the empty windows in initialization of the read iterator. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190627125152.54905-5-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: msu: Split sgt array and pointer in multiwindow modeAlexander Shishkin2019-07-031-10/+13
| | | | | | | | | | | To allow the use of externally allocated SG tables further down the line, change the code to reference the table via a pointer and make it point to the locally allocated table by default. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190627125152.54905-4-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: msu: Support multipage blocksAlexander Shishkin2019-07-031-18/+38
| | | | | | | | | | | | | | | Now that the MSU is using scatterlist, we can support multipage blocks. At the moment, the code assumes that all blocks are page-sized, but in larger buffers it may make sense to chunk together larger blocks of memory. One place where one-to-many relationship needs to be handled is the MSU buffer's mmap path. Get rid of the implicit assumption that all blocks are page-sized. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190627125152.54905-3-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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