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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2011-11-0394-3109/+3543
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits) MIPS: O32: Provide definition of registers ta0 .. ta3. MIPS: perf: Add Octeon support for hardware perf. MIPS: perf: Add support for 64-bit perf counters. MIPS: perf: Reorganize contents of perf support files. MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c MIPS: Add accessor macros for 64-bit performance counter registers. MIPS: Add probes for more Octeon II CPUs. MIPS: Add more CPU identifiers for Octeon II CPUs. MIPS: XLR, XLS: Add comment for smp setup MIPS: JZ4740: GPIO: Check correct IRQ in demux handler MIPS: JZ4740: GPIO: Simplify IRQ demuxer MIPS: JZ4740: Use generic irq chip MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines MIPS: Alchemy: kill au1xxx.h header MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep MIPS: Alchemy: Redo PCI as platform driver MIPS: Alchemy: more base address cleanup MIPS: Alchemy: rewrite USB platform setup. MIPS: Alchemy: abstract USB block control register access ... Fix up trivial conflicts in: arch/mips/alchemy/devboards/db1x00/platform.c drivers/ide/Kconfig drivers/mmc/host/au1xmmc.c drivers/video/Kconfig sound/mips/Kconfig
| * MIPS: O32: Provide definition of registers ta0 .. ta3.Ralf Baechle2011-10-251-0/+6
| | | | | | | | | | | | Later IRIX versions provide them in <sys/regdef.h> and gas also accepts $ta0 .. $ta3 since binutils 2.18 so Linux should do the same for source compatibility.
| * MIPS: perf: Add Octeon support for hardware perf.David Daney2011-10-252-1/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hardware counters for Octeon, and add the corresponding event mappings. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: perf: Add support for 64-bit perf counters.David Daney2011-10-251-469/+389
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hard coded constants are moved to struct mips_pmu. All counter register access move to the read_counter and write_counter function pointers, which are set to either 32-bit or 64-bit access methods at initialization time. Many of the function pointers in struct mips_pmu were not needed as there was only a single implementation, these were removed. I couldn't figure out what made struct cpu_hw_events.msbs[] at all useful, so I removed it too. Some functions and other declarations were reordered to reduce the need for forward declarations. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2792/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: perf: Reorganize contents of perf support files.David Daney2011-10-254-520/+532
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The contents of arch/mips/kernel/perf_event.c and arch/mips/kernel/perf_event_mipsxx.c were divided in a seemingly ad hoc manner, with the first including the second. I moved all the hardware counter support code to perf_event_mipsxx.c and removed the gating #ifdefs to the Kconfig and Makefile. Now perf_event.c contains only the callchain support, everything else is in perf_event_mipsxx.c There are no code changes, only moving of functions from one file to the other, or removing empty unneeded functions. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Dezhong Diao <dediao@cisco.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2791/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.cDavid Daney2011-10-252-57/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of a bunch of useless inline declarations, and join a bunch of improperly split lines. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2793/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Add accessor macros for 64-bit performance counter registers.David Daney2011-10-251-0/+8
| | | | | | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2789/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Add probes for more Octeon II CPUs.David Daney2011-10-251-0/+3
| | | | | | | | | | | | | | | | | | Detect cn61XX, cn66XX and cn68XX CPUs in cpu_probe_cavium(). Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2777/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Add more CPU identifiers for Octeon II CPUs.David Daney2011-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | The CPU identifiers for cn68XX, cn66XX and cn61XX are known, so add them. Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2776/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: XLR, XLS: Add comment for smp setupHillf Danton2011-10-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | It seems that BSP could be setup twice, but the nlm_cpu_ready array is only set for ASPs in smpboot.S, not including BSP. Signed-off-by: Hillf Danton <dhillf@gmail.com> Cc: "Jayachandran C." <jayachandranc@netlogicmicro.com> Cc: LKML <linux-kernel@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2695/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>,
| * MIPS: JZ4740: GPIO: Check correct IRQ in demux handlerLars-Peter Clausen2011-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | Check the trigger direction for the triggered IRQ instead of the parent IRQ. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/2433/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: JZ4740: GPIO: Simplify IRQ demuxerLars-Peter Clausen2011-10-251-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | We already know the base IRQ for a GPIO chip, so there is no need to recalculate it in the demux handler. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen <lars@metafoo.de> Patchwork: http://patchwork.linux-mips.org/patch/2432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: JZ4740: Use generic irq chipLars-Peter Clausen2011-10-255-153/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the generic irq chip framework to implement the jz4740 INTC and GPIO irq chips. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2434/ Patchwork: https://patchwork.linux-mips.org/patch/2771/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: remove all CONFIG_SOC_AU1??? definesManuel Lauss2011-10-2522-348/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | Now that no driver any longer depends on the CONFIG_SOC_AU1??? symbols, it's time to get rid of them: Move some of the platform devices to the boards which can use them, Rename a few (unused) constants in the header, Replace them with MIPS_ALCHEMY in the various Kconfig files. Finally delete them altogether from the Alchemy Kconfig file. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: kill au1xxx.h headerManuel Lauss2011-10-257-49/+11
| | | | | | | | | | | | | | | | | | | | | | No longer required Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/include/asm/mach-au1x00/au1xxx.h
| * MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? definesManuel Lauss2011-10-259-236/+207
| | | | | | | | | | | | | | | | | | | | This patch gets rid of all CONFIG_SOC_AU1XXX defines in DMA/DBDMA-related code. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header depManuel Lauss2011-10-256-24/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | au1xxx-ide uses defines from the pb1200/db1200 headers: get DBDMA ID through platform resource information, hardcode register spacing. The only 2 users of this driver (and the only boards it can really work on realiably) use the same register layout. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-ide@vger.kernel.org To: Linux-MIPS <linux-mips@linux-mips.org> Cc: linux-ide@vger.kernel.org Acked-by: David S. Miller <davem@davemloft.net> Patchwork: https://patchwork.linux-mips.org/patch/2716/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: Redo PCI as platform driverManuel Lauss2011-10-2519-625/+950
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rewrite Alchemy PCI support as a platform driver. - Fixup boards which have PCI. Run-tested on DB1500 and DB1550. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/pci.c delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c
| * MIPS: Alchemy: more base address cleanupManuel Lauss2011-10-2513-247/+146
| | | | | | | | | | | | | | | | | | | | remove all redundant peripheral base address defines, fix all affected boards and drivers. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: rewrite USB platform setup.Manuel Lauss2011-10-252-163/+75
| | | | | | | | | | | | | | | | | | | | | | | | Use runtime CPU detection to setup all USB parts. Remove the Au1200 OTG and UDC platform devices since there are no drivers for them anyway. Clean up the USB address mess in the au1000 header. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: abstract USB block control register accessManuel Lauss2011-10-257-281/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alchemy chips have one or more registers which control access to the usb blocks as well as PHY configuration. I don't want the OHCI/EHCI glues to know about the different registers and bits; new code hides the gory details of USB configuration from them. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: linux-usb@vger.kernel.org Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Patchwork: https://patchwork.linux-mips.org/patch/2709/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 drivers/usb/host/alchemy-common.c
| * MIPS: Remove __init from add_wired_entry()Manuel Lauss2011-10-252-4/+4
| | | | | | | | | | | | | | | | | | | | For Alchemy-PCI I need to add a wired entry after resuming from RAM; remove the __init from add_wired_entry() so that this actually works. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2684/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MMC: au1xmmc: Remove Alchemy CPU subtype dependenciesManuel Lauss2011-10-251-43/+50
| | | | | | | | | | | | | | | | | | | | | | Replace all occurrences of CONFIG_SOC_AU1??? with runtime feature detection. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: linux-mmc@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2683/ Acked-by: Chris Ball <cjb@laptop.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: support multiple GPIO styles in one kernelManuel Lauss2011-10-254-49/+100
| | | | | | | | | | | | | | | | | | | | | | For GPIOLIB=y decide at runtime which gpiochips to register; in the GPIOLIB=n case, the gpio headers need to be reshuffled a bit to make multiple implementations coexist peacefully. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: Always build power codeManuel Lauss2011-10-251-4/+0
| | | | | | | | | | | | | | | | | | No reason NOT to build it Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2678/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * NET: au1000_eth: Pass MACDMA address through platform resource info.Manuel Lauss2011-10-253-22/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the last hardcoded base address from the au1000_eth driver. The base address of the MACDMA unit was derived from the platform device id; if someone registered the MACs in inverse order both would not work. So instead pass the base address of the DMA unit to the driver with the other platform resource information. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Acked-by: David S. Miller <davem@davemloft.net> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2674/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Fix build with C=1Aaro Koskinen2011-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When trying to compile the 3.1-rc10 kernel for my MIPS board with C=1 (sparse checking), the build fails early with the error: CHK include/linux/version.h UPD include/linux/version.h CHK include/generated/utsrelease.h UPD include/generated/utsrelease.h Checking missing-syscalls for N32 CALL scripts/checksyscalls.sh Checking missing-syscalls for O32 CALL scripts/checksyscalls.sh CC kernel/bounds.s GEN include/generated/bounds.h CC arch/mips/kernel/asm-offsets.s GEN include/generated/asm-offsets.h CALL scripts/checksyscalls.sh HOSTCC scripts/genksyms/genksyms.o SHIPPED scripts/genksyms/lex.lex.c SHIPPED scripts/genksyms/keywords.hash.c SHIPPED scripts/genksyms/parse.tab.h HOSTCC scripts/genksyms/lex.lex.o SHIPPED scripts/genksyms/parse.tab.c HOSTCC scripts/genksyms/parse.tab.o HOSTLD scripts/genksyms/genksyms /bin/sh: Syntax error: "(" unexpected make[3]: *** [scripts/mod/empty.o] Error 2 make[2]: *** [scripts/mod] Error 2 make[1]: *** [scripts] Error 2 It seems the shell chokes because sparse is called with command line arguments such as: -D__INT8_C(c)='c' Converting these to form: -D'__INT8_C(c)'='c' seems to fix the problem. [ralf@linux-mips.org: This affects builds with gcc 4.5 and newer.] Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2827/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: MSP71xx: Fix build error.Ralf Baechle2011-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | After the recent cleanup of the register_*_smp_ops() functions msp71xx wasn't fixed to include the now necessary header resulting in: /home/ralf/src/linux/upstream-linus/arch/mips/pmc-sierra/msp71xx/msp_setup.c: In function ‘prom_init’: /home/ralf/src/linux/upstream-linus/arch/mips/pmc-sierra/msp71xx/msp_setup.c:231:2: error: implicit declaration of function ‘register_vsmp_smp_ops’ [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Don't install vmlinuz if compressed kernel has not been configured.Ralf Baechle2011-10-201-0/+2
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Netlogic: Specify architecture CFLAGSJayachandran C2011-10-201-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use -march=xlr if available, otherwise fallback to mips64. This allows us to support compilation with MIPS toolchains which are not customized for XLR. [ralf@linux-mips.org: And more importantly it works around a gas bug in binutils 2.21 which otherwise may result in an assertion failure building arch/mips/kernel/genex.S. See http://sourceware.org/bugzilla/show_bug.cgi?id=12915 for details.] Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2534/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS:Netlogic:Fix section mismatch warnings.Jayachandran C2011-10-203-8/+14
| | | | | | | | | | | | | | | | | | Add __init and __cpuinit annotation to functions that need it. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2535/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * Revert "MIPS: LD/SD o32 macro GAS fix update"Ralf Baechle2011-10-202-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 97475f8b42e83be2966aa2d70ab9c98477701c53 (lmo) / 82b89152f00f7ad17844d5614d5011e8d7944ac9 (kernel.org) [MIPS: LD/SD o32 macro GAS fix update]. Turns out this patch is producing many build errors with gcc 4.2. Based on further testing with a test case extracted from the build errors found further build errors and suboptimal generation even in violation of the "R" constraint. To make matters worse, the binutils changes also don't work quite as intended so revert this patch for now.
| * MIPS: SNI: Fix conflicting wrapper symbols for headers.Ralf Baechle2011-10-202-6/+6
| | | | | | | | | | | | | | | | | | | | If Open Firmware / Device Tree support is enabled on a SNI RM kernel both <asm/mipsprom.h> and <asm/prom.h> will be included into some .c files. Since both headers use the same wrapper symbol only the inclusion of the first file will have an effect but the 2nd file will be ignored resulting in a build error. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: PNX8550: Fix section mismatchRalf Baechle2011-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Triggered by pnx8550-jbs_defconfig and pnx8550-stb810_defconfig: WARNING: vmlinux.o(.text+0xc0c): Section mismatch in reference from the function prom_getcmdline() to the variable .init.data:arcs_cmdline The function prom_getcmdline() references the variable __initdata arcs_cmdline. This is often because prom_getcmdline lacks a __initdata annotation or the annotation of arcs_cmdline is wrong. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: 32-bit: Fix number of argument to epoll_wait.Ralf Baechle2011-10-201-1/+1
| | | | | | | | | | | | | | The number of arguments only matters for syscalls with stack arguments that is using 5 or more argument slots so this is just cosmetic fix. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: IP27: Sort out section mismatch.Ralf Baechle2011-10-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WARNING: vmlinux.o(.text+0x3059f8): Section mismatch in reference from the function pcibios_plat_dev_init() to the function .devinit.text:request_bridge_irq() The function pcibios_plat_dev_init() references the function __devinit request_bridge_irq(). This is often because pcibios_plat_dev_init lacks a __devinit annotation or the annotation of request_bridge_irq is wrong. Fixing this one leads to: WARNING: vmlinux.o(.text+0x1790): Section mismatch in reference from the function request_bridge_irq() to the function .devinit.text:register_bridge_irq() The function request_bridge_irq() references the function __devinit register_bridge_irq(). This is often because request_bridge_irq lacks a __devinit annotation or the annotation of register_bridge_irq is wrong. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: cache: Provide cache flush operations for XFSRalf Baechle2011-10-206-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | Until now flush_kernel_vmap_range() and invalidate_kernel_vmap_range() did not exist on MIPS resulting in heavy cache corruption on XFS filesystems. Left for the post-3.0 time: optimization and make this work with highmem, too. Since the combination of highmem + cache aliases atm doesn't work this isn't a regression. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2505/
| * MIPS: Lantiq: Fix MTD registration of NOR deviceJohn Crispin2011-10-201-2/+2
| | | | | | | | | | | | | | | | | | | | The 2 functions add_mtd_partitions and del_mtd_partitions were renamed to mtd_device_register and mtd_device_unregister. Signed-of-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2463/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | edac: Only build sb_edac on 64-bitJosh Boyer2011-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | The sb_edac driver is marginally useful on a 32-bit kernel, and currently has 64-bit divide compile errors when building that config. For now, make this build on only for 64-bit kernels. Signed-off-by: Josh Boyer <jwboyer@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'next' of git://github.com/kernelslacker/cpufreqLinus Torvalds2011-11-033-32/+268
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://github.com/kernelslacker/cpufreq: [CPUFREQ] db8500: support all frequencies [CPUFREQ] db8500: remove unneeded for loop iteration over freq_table [CPUFREQ] ARM Exynos4210 PM/Suspend compatibility with different bootloaders [CPUFREQ] ARM: ux500: send cpufreq notification for all cpus [CPUFREQ] e_powersaver: Allow user to lower maximum voltage [CPUFREQ] e_powersaver: Check BIOS limit for CPU frequency [CPUFREQ] e_powersaver: Additional checks [CPUFREQ] exynos4210: Show list of available frequencies
| * | [CPUFREQ] db8500: support all frequenciesLinus Walleij2011-10-261-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the 200 MHz frequency mode of the DB8500 SoC, and prints the available frequencies at init time. Cc: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] db8500: remove unneeded for loop iteration over freq_tableAxel Lin2011-10-261-5/+0
| | | | | | | | | | | | | | | | | | | | | Don't know why to do the loop iteration here. It looks unneeded. Signed-off-by: Axel Lin <axel.lin@gmail.com> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] ARM Exynos4210 PM/Suspend compatibility with different bootloadersMyungJoo Ham2011-10-261-4/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have various bootloaders for Exynos4210 machines. Some of they set the ARM core frequency at boot time even when the boot is a resume from suspend-to-RAM. Such changes may create inconsistency in the data of CPUFREQ driver and have incurred hang issues with suspend-to-RAM. This patch enables to save and restore CPU frequencies with pm-notifier and sets the frequency at the initial (boot-time) value so that there wouldn't be any inconsistency between bootloader and kernel. This patch does not use CPUFREQ's suspend/resume callbacks because they are syscore-ops, which do not allow to use mutex that is being used by regulators that are used by the target function. This also prevents any CPUFREQ transitions during suspend-resume context, which could be dangerous at noirq-context along with regulator framework. Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] ARM: ux500: send cpufreq notification for all cpusVincent Guittot2011-10-261-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The same clock is used for all cpus so we must notify the frequency change for each one in order to update the configuration of all twd clockevents. change since V1: * use policy->cpus instead of cpu_online_mask Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] e_powersaver: Allow user to lower maximum voltageRafał Bilski2011-10-261-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new module option "set_max_voltage". One of the lessons learned from Adaptive Powersaver is that voltage values returned by processor are for worst case scenario. But required voltage is changing with CPU temperature. And even processors produced in the same batch can have different minimum voltage necessary for stable work at specified frequency. On Elonex Webbook, once system starts, temperature never drops below 48 deg. C. Loading module after systems start allows user to lower CPU voltage and still have stable system. Sadly C7 doesn't allow code to set frequency or voltage from outside limits. If you ask it to set voltage lower then minimum it will ignore you. Thats why it isn't possible to change minimum voltage for minimum frequency too. Changing maximum voltage on Elonex Webbook leads to very good results. Looks like VIA C7 1.6GHz 1084mV can safetly run at 892mV. This means 83% of orginal value. If same percentage applies to power generated it means 12.5W in the place of 15W. Not much, but it is better then nothing. Only C7-M makes it possible. If voltage is too low by 16mV or more you will experience kernel panic. If voltage is too low by 32mV or more you will experience system freeze. Signed-off-by: Rafał Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] e_powersaver: Check BIOS limit for CPU frequencyRafał Bilski2011-10-261-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call ACPI function to get BIOS limit for CPU frequency. Fail if processor would like to run at higher frequency. Allow user to ignore BIOS limit. eps: Detected VIA Model D C7-M eps: Current voltage = 1084mV eps: Current multiplier = 16 eps: Highest voltage = 1084mV eps: Highest multiplier = 16 eps: Lowest voltage = 844mV eps: Lowest multiplier = 4 eps: ACPI limit 1.60GHz Signed-off-by: Rafał Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] e_powersaver: Additional checksRafał Bilski2011-10-261-11/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some systems are using 1,2Ghz@844mV processors running at 600MHz@796mV. Try to detect such systems and don't touch anything on it. If CPU doesn't have P-States in BIOS it should run at maximum frequency. Allow user to bypass checks by means of two new options. Don't set frequency to maximum on module unloading to avoid bada boom. It is also possible that some processors may have incorrect values in min/max registers caused by error in manufacturing process. Probably it would be BIOS job to set them to right frequency and P-States tables would have correct values inside. Two additional sanity checks for voltage. Signed-off-by: Rafał Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] exynos4210: Show list of available frequenciesDonggeun Kim2011-10-261-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables 'scaling_available_frequencies' attribute showing list of available frequencies. Signed-off-by: Donggeun Kim <dg77.kim@samsung.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: KyungMin Park <kyungmin.park@samsung.com> Signed-off-by: Dave Jones <davej@redhat.com>
* | | Merge branch 'for-next' of git://git.infradead.org/users/sameo/mfd-2.6Linus Torvalds2011-11-0374-2730/+6038
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-next' of git://git.infradead.org/users/sameo/mfd-2.6: (80 commits) mfd: Fix missing abx500 header file updates mfd: Add missing <linux/io.h> include to intel_msic x86, mrst: add platform support for MSIC MFD driver mfd: Expose TurnOnStatus in ab8500 sysfs mfd: Remove support for early drop ab8500 chip mfd: Add support for ab8500 v3.3 mfd: Add ab8500 interrupt disable hook mfd: Convert db8500-prcmu panic() into pr_crit() mfd: Refactor db8500-prcmu request_clock() function mfd: Rename db8500-prcmu init function mfd: Fix db5500-prcmu defines mfd: db8500-prcmu voltage domain consumers additions mfd: db8500-prcmu reset code retrieval mfd: db8500-prcmu tweak for modem wakeup mfd: Add db8500-pcmu watchdog accessor functions for watchdog mfd: hwacc power state db8500-prcmu accessor mfd: Add db8500-prcmu accessors for PLL and SGA clock mfd: Move to the new db500 PRCMU API mfd: Create a common interface for dbx500 PRCMU drivers mfd: Initialize DB8500 PRCMU regs ... Fix up trivial conflicts in arch/arm/mach-imx/mach-mx31moboard.c arch/arm/mach-omap2/board-omap3beagle.c arch/arm/mach-u300/include/mach/irqs.h drivers/mfd/wm831x-spi.c
| * | | mfd: Fix missing abx500 header file updatesLinus Walleij2011-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I missed to include a patch adding the new silicon revision define CUT3P3 and remove the retired CUT0 versions of AB8500. Also delete the reference to the retired AB3550 from the header. Reported-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-11 14:35:32 +0100