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* KEYS: asym_tpm: Implement encryption operation [ver #2]Denis Kenzior2018-10-261-0/+84
* KEYS: asym_tpm: Implement pkey_query [ver #2]Denis Kenzior2018-10-261-0/+135
* KEYS: Add parser for TPM-based keys [ver #2]Denis Kenzior2018-10-264-0/+127
* KEYS: asym_tpm: extract key size & public key [ver #2]Denis Kenzior2018-10-262-0/+115
* KEYS: asym_tpm: add skeleton for asym_tpm [ver #2]Denis Kenzior2018-10-264-0/+118
* crypto: rsa-pkcs1pad: Allow hash to be optional [ver #2]Denis Kenzior2018-10-261-18/+41
* KEYS: Implement PKCS#8 RSA Private Key parser [ver #2]David Howells2018-10-265-0/+233
* KEYS: Implement encrypt, decrypt and sign for software asymmetric key [ver #2]David Howells2018-10-261-1/+81
* KEYS: Allow the public_key struct to hold a private key [ver #2]David Howells2018-10-262-2/+13
* KEYS: Provide software public key query function [ver #2]David Howells2018-10-261-17/+82
* KEYS: Make the X.509 and PKCS7 parsers supply the sig encoding type [ver #2]David Howells2018-10-262-12/+10
* KEYS: Provide missing asymmetric key subops for new key type ops [ver #2]David Howells2018-10-266-7/+180
* KEYS: Provide keyctls to drive the new key type ops for asymmetric keys [ver #2]David Howells2018-10-267-0/+541
* KEYS: Provide key type operations for asymmetric key ops [ver #2]David Howells2018-10-264-0/+168
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparcLinus Torvalds2018-10-267-62/+335
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| * sparc: Fix VDSO build with older binutils.David S. Miller2018-10-257-62/+335
* | Merge tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-2633-246/+1039
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| * \ RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-2312-70/+259
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| | * | RISC-V: Show IPI statsAnup Patel2018-10-233-7/+49
| | * | RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel2018-10-231-4/+6
| | * | RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-238-32/+71
| | * | RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-233-1/+46
| | * | RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra2018-10-231-2/+3
| | * | RISC-V: Use mmgrab()Palmer Dabbelt2018-10-231-1/+2
| | * | RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt2018-10-231-4/+5
| | * | RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-235-6/+9
| | * | RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt2018-10-231-10/+4
| | * | RISC-V: Disable preemption before enabling interruptsAtish Patra2018-10-231-1/+5
| | * | RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt2018-10-231-0/+4
| | * | RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt2018-10-231-7/+61
| | * | RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt2018-10-231-7/+0
| | * | RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2018-10-232-3/+2
| * | | RISC-V: Fix some RV32 bugs and build failuresPalmer Dabbelt2018-10-238-2/+353
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| | * | | RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremapVincent Chen2018-10-231-1/+1
| | * | | RISC-V: Select GENERIC_LIB_UMODDI3 on RV32Zong Li2018-10-231-0/+1
| | * | | lib: Add umoddi3 and udivmoddi4 of GCC library routinesZong Li2018-10-234-0/+346
| | * | | RISC-V: Use swiotlb on RV64 onlyZong Li2018-10-231-0/+3
| | * | | RISC-V: Build tishift only on 64-bitZong Li2018-10-231-1/+2
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| * | | riscv: Add support to no-FPU systemsPalmer Dabbelt2018-10-239-127/+196
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| | * | | Auto-detect whether a FPU existsAlan Kao2018-10-234-7/+19
| | * | | Allow to disable FPU supportAlan Kao2018-10-236-3/+29
| | * | | Cleanup ISA string settingAlan Kao2018-10-231-11/+8
| | * | | Refactor FPU code in signal setup/return proceduresAlan Kao2018-10-231-27/+41
| | * | | Extract FPU context operations from entry.SAlan Kao2018-10-233-87/+107
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| * | | RISC-V: Cosmetic menuconfig changesNick Kossifidis2018-10-232-36/+39
| * | | riscv: move GCC version check for ARCH_SUPPORTS_INT128 to KconfigMasahiro Yamada2018-10-232-2/+1
| * | | RISC-V: remove the unused return_to_handler exportChristoph Hellwig2018-10-231-1/+0
| * | | RISC-V: Add futex support.Jim Wilson2018-10-233-1/+129
| * | | RISC-V: Add FP register ptrace support for gdb.Jim Wilson2018-10-232-0/+55
| * | | RISC-V: Mask out the F extension on systems without DPalmer Dabbelt2018-10-231-0/+7
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