summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'remotes/lorenzo/pci/uniphier'Bjorn Helgaas2019-01-025-0/+570
|\ | | | | | | | | | | | | | | | | | | | | | | - Add UniPhier PCIe controller driver and DT bindings (Kunihiko Hayashi) * remotes/lorenzo/pci/uniphier: PCI: uniphier: Add UniPhier PCIe host controller support dt-bindings: PCI: Add UniPhier PCIe host controller description # Conflicts: # drivers/pci/controller/dwc/Kconfig # drivers/pci/controller/dwc/Makefile
| * PCI: uniphier: Add UniPhier PCIe host controller supportKunihiko Hayashi2018-12-194-0/+489
| | | | | | | | | | | | | | | | | | This introduces specific glue layer for UniPhier platform to support PCIe host controller that is based on the DesignWare PCIe core, and this driver supports Root Complex (host) mode. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * dt-bindings: PCI: Add UniPhier PCIe host controller descriptionKunihiko Hayashi2018-12-191-0/+81
| | | | | | | | | | | | | | | | | | | | Add DT bindings for PCIe controller implemented in UniPhier SoCs when configured in Root Complex (host) mode. This controller is based on the DesignWare PCIe core. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
* | Merge branch 'remotes/lorenzo/pci/mediatek'Bjorn Helgaas2019-01-024-95/+27
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use devm resource parser in mediatek (Honghui Zhang) - Remove unused mediatek "num-lanes" DT property (Honghui Zhang) * remotes/lorenzo/pci/mediatek: arm64: dts: mt7622: Remove un-used property for PCIe arm: dts: mt7623: Remove un-used property for PCIe dt-bindings: PCI: MediaTek: Remove un-used property PCI: mediatek: Remove un-used variant in struct mtk_pcie_port PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DT
| * | arm64: dts: mt7622: Remove un-used property for PCIeHonghui Zhang2018-12-181-2/+0
| | | | | | | | | | | | | | | | | | | | | The "num-lanes" property for PCIe is not used, remove it. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | arm: dts: mt7623: Remove un-used property for PCIeHonghui Zhang2018-12-181-3/+0
| | | | | | | | | | | | | | | | | | | | | The "num-lanes" property for PCIe is not used, remove it. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | dt-bindings: PCI: MediaTek: Remove un-used propertyHonghui Zhang2018-12-181-8/+0
| | | | | | | | | | | | | | | | | | | | | The "num-lanes" property is not used, remove it. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: mediatek: Remove un-used variant in struct mtk_pcie_portHonghui Zhang2018-12-181-8/+0
| | | | | | | | | | | | | | | | | | | | | The "lane" variant in struct mtk_pcie_port is not used, remove it. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DTHonghui Zhang2018-11-301-74/+27
| |/ | | | | | | | | | | | | | | | | Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF DT parser. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
* | Merge branch 'remotes/lorenzo/pci/dwc-msi'Bjorn Helgaas2019-01-021-13/+24
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Mask DesignWare interrupts instead of disabling them to avoid lost interrupts (Marc Zyngier) - Add locking when acking DesignWare interrupts (Marc Zyngier) - Ack DesignWare interrupts in the proper callbacks (Marc Zyngier) * remotes/lorenzo/pci/dwc-msi: PCI: dwc: Move interrupt acking into the proper callback PCI: dwc: Take lock when ACKing an interrupt PCI: dwc: Use interrupt masking instead of disabling
| * | PCI: dwc: Move interrupt acking into the proper callbackMarc Zyngier2018-12-111-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The write to the status register is really an ACK for the HW, and should be treated as such by the driver. Let's move it to the irq_ack() callback, which will prevent people from moving it around in order to paper over other bugs. Fixes: 8c934095fa2f ("PCI: dwc: Clear MSI interrupt status after it is handled, not before") Fixes: 7c5925afbc58 ("PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API") Link: https://lore.kernel.org/linux-pci/20181113225734.8026-1-marc.zyngier@arm.com/ Reported-by: Trent Piepho <tpiepho@impinj.com> Tested-by: Niklas Cassel <niklas.cassel@linaro.org> Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Tested-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org
| * | PCI: dwc: Take lock when ACKing an interruptMarc Zyngier2018-12-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bizarrely, there is no lock taken in the irq_ack() helper. This puts the ACK callback provided by a specific platform in a awkward situation where there is no synchronization that would be expected on other callback. Introduce the required lock, giving some level of uniformity among callbacks. Fixes: 7c5925afbc58 ("PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API") Link: https://lore.kernel.org/linux-pci/20181113225734.8026-1-marc.zyngier@arm.com/ Tested-by: Niklas Cassel <niklas.cassel@linaro.org> Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Tested-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org
| * | PCI: dwc: Use interrupt masking instead of disablingMarc Zyngier2018-12-111-7/+12
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwc driver is showing an interesting level of brokeness, as it insists on using the enable/disable set of registers to mask/unmask MSIs, meaning that an MSIs being generated while the interrupt is in that "disabled" state will simply be lost. Let's move to the mask/unmask set of registers, which offers the expected semantics. Fixes: 7c5925afbc58 ("PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API") Link: https://lore.kernel.org/linux-pci/20181113225734.8026-1-marc.zyngier@arm.com/ Tested-by: Niklas Cassel <niklas.cassel@linaro.org> Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Tested-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org
* | Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas2019-01-0212-23/+150
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Constify histb dw_pcie_host_ops structure (Julia Lawall) - Support multiple power domains for imx6 (Leonard Crestez) - Constify layerscape driver data (Stefan Agner) - Update imx6 Kconfig to allow imx6 PCIe in imx7 kernel (Trent Piepho) - Support armada8k GPIO reset (Baruch Siach) - Support suspend/resume support on imx6 (Leonard Crestez) - Don't hard-code DesignWare DBI/ATU offst (Stephen Warren) - Skip i.MX6 PHY setup on i.MX7D (Andrey Smirnov) - Remove Jianguo Sun from HiSilicon STB maintainers (Lorenzo Pieralisi) * remotes/lorenzo/pci/dwc: MAINTAINERS: Remove Jianguo Sun from HiSilicon STB DWC entry PCI: dwc: Don't hard-code DBI/ATU offset PCI: imx: Add imx6sx suspend/resume support PCI: armada8k: Add support for gpio controlled reset signal PCI: dwc: Adjust Kconfig to allow IMX6 PCIe host on IMX7 PCI: dwc: layerscape: Constify driver data PCI: imx: Add multi-pd support dt-bindings: imx6q-pcie: Add multi-pd bindings for imx6sx PCI: histb: Constify dw_pcie_host_ops structure
| * | MAINTAINERS: Remove Jianguo Sun from HiSilicon STB DWC entryLorenzo Pieralisi2018-12-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jianguo Sun's email address reported in MAINTAINERS is not active any longer, remove it from the DWC HiSilicon STB entry. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Shawn Guo <shawn.guo@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org>
| * | PCI: dwc: Don't hard-code DBI/ATU offsetStephen Warren2018-12-184-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DWC PCIe core contains various separate register spaces: DBI, DBI2, ATU, DMA, etc. The relationship between the addresses of these register spaces is entirely determined by the implementation of the IP block, not by the IP block design itself. Hence, the DWC driver must not make assumptions that one register space can be accessed at a fixed offset from any other register space. To avoid such assumptions, introduce an explicit/separate register pointer for the ATU register space. In particular, the current assumption is not valid for NVIDIA's T194 SoC. The ATU register space is only used on systems that require unrolled ATU access. This property is detected at run-time for host controllers, and when this is detected, this patch provides a default value for atu_base that matches the previous assumption re: register layout. An alternative would be to update all drivers for HW that requires unrolled access to explicitly set atu_base. However, it's hard to tell which drivers would require atu_base to be set. The unrolled property is not detected for endpoint systems, and so any endpoint driver that requires unrolled access must explicitly set the iatu_unroll_enabled flag (none do at present), and so a check is added to require the driver to also set atu_base while at it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Acked-by: Vidya Sagar <vidyas@nvidia.com>
| * | PCI: imx: Add imx6sx suspend/resume supportLeonard Crestez2018-12-182-5/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PCI suspend/resume support on imx6sx SOCs. This is similar to imx7d with a few differences: * The PM_Turn_Off bit is exposed through an IOMUX GPR, like all other pcie control bits on 6sx. * The pcie_inbound_axi clk needs to be turned off in suspend. On resume it is restored via resume -> deassert_core_reset -> enable_ref_clk. Most of the resume logic is shared with the initial reset after probe. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de>
| * | PCI: armada8k: Add support for gpio controlled reset signalBaruch Siach2018-12-181-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the gpio reset signal binding as described in the designware-pcie.txt DT binding document. Both the documented 'reset-gpio' property name and the more standard 'reset-gpios' name are supported. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * | PCI: dwc: Adjust Kconfig to allow IMX6 PCIe host on IMX7Trent Piepho2018-12-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6 PCI-e host driver also supports the IMX7d. However, the Kconfig dependencies of the driver prevented it from being enabled unless the kernel was built with both IMX6 and IMX7 support. It works fine to build with only IMX7 support enabled therefore adjust the Kconfig entry to allow this configuration. Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
| * | PCI: dwc: layerscape: Constify driver dataStefan Agner2018-12-181-5/+5
| | | | | | | | | | | | | | | | | | | | | Constify driver data since they do not get changed at runtime. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: imx: Add multi-pd supportLeonard Crestez2018-12-181-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some chips the PCIe and PCIE_PHY blocks are in separate power domains which can be power-gated independently. The PCI driver needs to handle this by keeping both domain active. This is intended for imx6sx where PCIe is in DISPLAY and PCIE_PHY in its own domain. Defining the DISPLAY domain requires a way for PCIe to keep it active or it will break when displays are off. The power-domains on imx6sx are meant to look like this: power-domains = <&pd_disp>, <&pd_pci>; power-domain-names = "pcie", "pcie_phy"; Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | dt-bindings: imx6q-pcie: Add multi-pd bindings for imx6sxLeonard Crestez2018-11-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe and PCIE_PHY blocks are in different power domains on imx6sx and this needs to be described using multi-pd bindings. This was not required until now because the power-domain of the PCIe block (DISPLAY) was always on. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
| * | PCI: histb: Constify dw_pcie_host_ops structureJulia Lawall2018-11-081-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | The dw_pcie_host_ops structure is only stored in the ops field of a pcie_port structure, and this field is const, so make the dw_pcie_host_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge branch 'remotes/lorenzo/pci/amlogic'Bjorn Helgaas2019-01-025-0/+680
|\ \ | | | | | | | | | | | | | | | | | | | | | - Add Amlogic Meson PCIe controller driver and DT bindings (Yue Wang) * remotes/lorenzo/pci/amlogic: PCI: amlogic: Add the Amlogic Meson PCIe controller driver dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
| * | PCI: amlogic: Add the Amlogic Meson PCIe controller driverYue Wang2018-12-194-0/+610
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Link: https://lore.kernel.org/linux-pci/20181218224708.GB22610@google.com/ Signed-off-by: Yue Wang <yue.wang@amlogic.com> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> [lorenzo.pieralisi@arm.com: updated coding/comment style] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controllerYue Wang2018-12-191-0/+70
| |/ | | | | | | | | | | | | | | | | | | | | The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds documentation for the DT bindings in Meson PCIe controller. Signed-off-by: Yue Wang <yue.wang@amlogic.com> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
* | Merge branch 'pci/virtualization'Bjorn Helgaas2019-01-023-12/+40
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | - Skip VF scanning on powerpc, which does this in firmware (Sebastian Ott) * pci/virtualization: s390/pci: skip VF scanning PCI/IOV: Add flag so platforms can skip VF scanning PCI/IOV: Factor out sriov_add_vfs()
| * | s390/pci: skip VF scanningSebastian Ott2019-01-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Set the flag to skip scanning for VFs after SR-IOV enablement. VF creation will be triggered by the hotplug code. Signed-off-by: Sebastian Ott <sebott@linux.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/IOV: Add flag so platforms can skip VF scanningSebastian Ott2019-01-022-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a flag to skip scanning for new VFs after SR-IOV enablement. This can be set by implementations for which the VFs are already reported by other means. Signed-off-by: Sebastian Ott <sebott@linux.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/IOV: Factor out sriov_add_vfs()Sebastian Ott2019-01-021-13/+31
| |/ | | | | | | | | | | | | | | Provide sriov_add_vfs() as a wrapper to scan for VFs that cleans up after itself. This is just a code simplification. No functional change. Signed-off-by: Sebastian Ott <sebott@linux.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
* | Merge branch 'pci/switchtec'Bjorn Helgaas2019-01-022-17/+153
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove status check after submitting Switchtec MRPC Firmware Download commands to avoid Completion Timeouts (Kelvin Cao) - Set Switchtec coherent DMA mask to allow 64-bit DMA (Boris Glimcher) - Fix Switchtec SWITCHTEC_IOCTL_EVENT_IDX_ALL flag overwrite issue (Joey Zhang) - Enable write combining for Switchtec MRPC Input buffers (Kelvin Cao) - Add Switchtec MRPC DMA mode support (Wesley Sheng) * pci/switchtec: switchtec: Add MRPC DMA mode support switchtec: Improve MRPC efficiency by enabling write combining switchtec: Fix SWITCHTEC_IOCTL_EVENT_IDX_ALL flags overwrite switchtec: Set DMA coherent mask switchtec: Remove immediate status check after submitting MRPC command
| * | switchtec: Add MRPC DMA mode supportWesley Sheng2018-12-132-10/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MRPC normal mode requires the host to read the MRPC command status and output data from BAR. This results in high latency responses from the Memory Read TLP and potential Completion Timeout (CTO). Add support for MRPC DMA mode, including related macro definitions and data structures and code to: * Retrieve MRPC DMA mode version from adapter firmware * Allocate DMA buffer, register ISR, and enable DMA during init * Check MRPC execution status and get execution results from DMA buffer * Release DMA buffer and disable DMA function when unloading module MRPC DMA mode is a new feature of firmware, and the driver will fall back to MRPC normal mode if there is no support in the legacy firmware. Add a module parameter, "use_dma_mrpc", to select between MRPC DMA mode and MRPC normal mode. Since the driver automatically detects DMA support in the firmware, this parameter is just for debugging and testing. Include <linux/io-64-nonatomic-lo-hi.h> so that readq/writeq is replaced by two readl/writel on systems that do not support it. Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> [bhelgaas: changelog, simplify dma_ver check] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
| * | switchtec: Improve MRPC efficiency by enabling write combiningKelvin Cao2018-12-131-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MRPC Input buffer is mostly memory without any side effects, so we can improve the access time by enabling write combining on this region of the BAR. In a few places, we still need to flush the WC buffer. To do this, we simply read from the Outbound Doorbell register because reads to this register are processed by low latency hardware. Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
| * | switchtec: Fix SWITCHTEC_IOCTL_EVENT_IDX_ALL flags overwriteJoey Zhang2018-12-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the ioctl_event_ctl() SWITCHTEC_IOCTL_EVENT_IDX_ALL case, we call event_ctl() several times with the same "ctl" struct. Each call clobbers ctl.flags, which leads to the problem that we may not actually enable or disable all events as the user requested. Preserve the event flag value with a temporary variable. Fixes: 52eabba5bcdb ("switchtec: Add IOCTLs to the Switchtec driver") Signed-off-by: Joey Zhang <joey.zhang@microchip.com> Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
| * | switchtec: Set DMA coherent maskBoris Glimcher2018-12-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Switchtec hardware supports 64-bit DMA, so set the correct DMA mask. This allows the CMA to allocate larger buffers for memory windows. Signed-off-by: Boris Glimcher <Boris.Glimcher@emc.com> Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
| * | switchtec: Remove immediate status check after submitting MRPC commandKelvin Cao2018-12-121-4/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After submitting a Firmware Download MRPC command, Switchtec firmware will delay Management EP BAR MemRd TLP responses by more than 10ms. This is a firmware limitation. Delayed MemRd completions are a problem for systems with a low Completion Timeout (CTO). The current driver checks the MRPC status immediately after submitting an MRPC command, which results in a delayed MemRd completion that may cause a Completion Timeout. Remove the immediate status check and rely on the check after receiving an interrupt or timing out. This is only a software workaround to the READ issue and a proper fix of this should be done in firmware. Fixes: 080b47def5e5 ("MicroSemi Switchtec management interface driver") Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
* | Merge branch 'pci/pm'Bjorn Helgaas2019-01-021-15/+12
|\ \ | | | | | | | | | | | | | | | | | | | | | - Allow runtime PM even if driver doesn't supply callbacks (Jarkko Nikula) * pci/pm: PCI / PM: Allow runtime PM without callback functions
| * | PCI / PM: Allow runtime PM without callback functionsJarkko Nikula2018-12-121-15/+12
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a9c8088c7988 ("i2c: i801: Don't restore config registers on runtime PM") nullified the runtime PM suspend/resume callback pointers while keeping the runtime PM enabled. This caused the SMBus PCI device to stay in D0 with /sys/devices/.../power/runtime_status showing "error" when the runtime PM framework attempted to autosuspend the device. This is due to PCI bus runtime PM, which checks for driver runtime PM callbacks and returns -ENOSYS if they are not set. Since i2c-i801.c doesn't need to do anything device-specific for runtime PM, Jean Delvare proposed this be fixed in the PCI core rather than adding dummy runtime PM callback functions in the PCI drivers. Change pci_pm_runtime_suspend()/pci_pm_runtime_resume() so they allow changing the PCI device power state during runtime PM transitions even if the driver supplies no runtime PM callbacks. This fixes the runtime PM regression on i2c-i801.c. It is not obvious why the code previously required the runtime PM callbacks. The test has been there since the code was introduced by 6cbf82148ff2 ("PCI PM: Run-time callbacks for PCI bus type"). On the other hand, a similar change was done to generic runtime PM callbacks in 05aa55dddb9e ("PM / Runtime: Lenient generic runtime pm callbacks"). Fixes: a9c8088c7988 ("i2c: i801: Don't restore config registers on runtime PM") Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: stable@vger.kernel.org # v4.18+
* | Merge branch 'pci/peer-to-peer'Bjorn Helgaas2019-01-022-9/+9
|\ \ | | | | | | | | | | | | | | | | | | - Clean up P2PDMA documentation (Randy Dunlap) * pci/peer-to-peer: PCI/P2PDMA: Clean up documentation and kernel-doc
| * | PCI/P2PDMA: Clean up documentation and kernel-docRandy Dunlap2018-12-112-9/+9
| |/ | | | | | | | | | | | | | | | | | | Fix typos, spellos, and grammar in p2pdma.rst and p2pdma.c. Fix return value(s) in function pci_p2pmem_alloc_sgl(). Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Logan Gunthorpe <logang@deltatee.com> Cc: Jonathan Corbet <corbet@lwn.net>
* | Merge branch 'pci/misc'Bjorn Helgaas2019-01-028-18/+44
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Expand Kconfig "PF" acronyms (Randy Dunlap) - Update MAINTAINERS for arch/x86/kernel/early-quirks.c (Bjorn Helgaas) - Add missing include to drivers/pci.h (Alexandru Gagniuc) - Override Synopsys USB 3.x HAPS device class so dwc3-haps can claim it instead of xhci (Thinh Nguyen) * pci/misc: PCI: Override Synopsys USB 3.x HAPS device class PCI: Move Synopsys HAPS platform device IDs PCI: Add missing include to drivers/pci.h PCI: Remove unnecessary space before function pointer arguments MAINTAINERS: Add x86 early-quirks.c file pattern to PCI subsystem PCI: Expand the "PF" acronym in Kconfig help text
| * | PCI: Override Synopsys USB 3.x HAPS device classThinh Nguyen2018-12-171-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synopsys USB 3.x host HAPS platform has a class code of PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these devices should use dwc3-haps driver. Change these devices' class code to PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming them. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Move Synopsys HAPS platform device IDsThinh Nguyen2018-12-172-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | Move Synopsys HAPS platform device IDs to pci_ids.h so that both drivers/pci/quirks.c and dwc3-haps driver can reference these IDs. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * | PCI: Add missing include to drivers/pci.hAlexandru Gagniuc2018-12-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This file makes use of definitions provided in <linux/pci.h>. This only compiles when <linux/pci.h> is included beforehand, and creates a nasty include dependency. Instead, just include the correct file. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Remove unnecessary space before function pointer argumentsBenjamin Young2018-12-062-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | Make spacing more consistent in the code for function pointer declarations based on checkpatch.pl. Signed-off-by: Benjamin Young <youngcdev@gmail.com> [bhelgaas: make similar changes in include/linux/pci.h] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | MAINTAINERS: Add x86 early-quirks.c file pattern to PCI subsystemBjorn Helgaas2018-11-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/x86/kernel/early-quirks.c contains special PCI quirks that need to run even before the usual DECLARE_PCI_FIXUP_EARLY() quirks. These have typically been merged by the x86 maintainers, which is fine, but PCI folks should at least see what's happening, so add a file pattern to the PCI subsystem entry. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ingo Molnar <mingo@kernel.org>
| * | PCI: Expand the "PF" acronym in Kconfig help textRandy Dunlap2018-11-051-3/+3
| |/ | | | | | | | | | | | | | | | | Tell users what a PCI PF is in the PCI_PF_STUB config help text. Fixes: a8ccf8a66663 ("PCI/IOV: Add pci-pf-stub driver for PFs that only enable VFs") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alexander Duyck <alexander.h.duyck@linux.intel.com>
* | Merge branch 'pci/enumeration'Bjorn Helgaas2019-01-021-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | - Fix Broadcom CNB20LE host bridge unintended sign extension (Colin Ian King) * pci/enumeration: x86/PCI: Fix Broadcom CNB20LE unintended sign extension (redux)
| * | x86/PCI: Fix Broadcom CNB20LE unintended sign extension (redux)Colin Ian King2018-11-091-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | In the expression "word1 << 16", word1 starts as u16, but is promoted to a signed int, then sign-extended to resource_size_t, which is probably not what was intended. Cast to resource_size_t to avoid the sign extension. This fixes an identical issue as fixed by commit 0b2d70764bb3 ("x86/PCI: Fix Broadcom CNB20LE unintended sign extension") back in 2014. Detected by CoverityScan, CID#138749, 138750 ("Unintended sign extension") Fixes: 3f6ea84a3035 ("PCI: read memory ranges out of Broadcom CNB20LE host bridge") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
* | Merge branch 'pci/aspm'Bjorn Helgaas2019-01-021-6/+0
|\ \ | |/ |/| | | | | | | | | - Remove unused lists from ASPM pcie_link_state (Frederick Lawler) * pci/aspm: PCI/ASPM: Remove unused lists from struct pcie_link_state
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 17:14:07 +0100