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* MIPS: Separate XPA CPU feature into LPA and MVHJames Hogan2016-05-133-2/+11
| | | | | | | | | | | | | | | | | | | | | | | XPA (eXtended Physical Addressing) should be detected as a combination of two architectural features: - Large Physical Address (as per Config3.LPA). With XPA this will be set on MIPS32r5 cores, but it may also be set for MIPS64r2 cores too. - MTHC0/MFHC0 instructions (as per Config5.MVH). With XPA this will be set, but it may also be set in VZ guest context even when Config3.LPA in the guest context has been cleared by the hypervisor. As such, XPA is only usable if both bits are set. Update CPU features to separate these two features, with cpu_has_xpa requiring both to be set. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13112/ Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix jalr emulation when rd == $0Paul Burton2016-05-131-3/+5
| | | | | | | | | | | | | | | | | | | | When emulating a jalr instruction with rd == $0, the code in isBranchInstr was incorrectly writing to GPR $0 which should actually always remain zeroed. This would lead to any further instructions emulated which use $0 operating on a bogus value until the task is next context switched, at which point the value of $0 in the task context would be restored to the correct zero by a store in SAVE_SOME. Fix this by not writing to rd if it is $0. Fixes: 102cedc32a6e ("MIPS: microMIPS: Floating point support.") Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable <stable@vger.kernel.org> # v3.10 Patchwork: https://patchwork.linux-mips.org/patch/13160/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix m{add,sub}.s shiftsPaul Burton2016-05-135-19/+25
| | | | | | | | | | | | | | | | | | | The code in _sp_maddf (formerly ieee754sp_madd) appears to have been copied verbatim from ieee754sp_add, and although it's adding the unpacked "r" & "z" floats it kept using macros that operate on "x" & "y". This led to the addition being carried out incorrectly on some mismash of the product, accumulator & multiplicand fields. Typically this would lead to the assertions "ze == re" & "ze <= SP_EMAX" failing since ze & re hadn't been operated upon. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction") Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13159/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix code indentationPaul Burton2016-05-132-2/+2
| | | | | | | | | | | | | | A line incrementing the re variable was indented a level too deep in ieee754dp_mul, making the code unclear to read. Fix the indentation. This appears to have been copied verbatim along with the rest of the multiplication code to ieee754dp_maddf, now _dp_maddf, too so fix the indentation there too. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13158/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix bit-width in ieee754dp_{mul, maddf, msubf} commentsPaul Burton2016-05-132-2/+2
| | | | | | | | | | | | | | | | | | A comment in ieee754dp_mul indicates that the code is about to perform a 32b x 32b multiplication & keep the high 32b of the result. It appears this was copied from the single-precision multiplication code, since the code actually goes on to perform a 64b x 64b multiplication & keep the high 64b of the result. Fix the comment to indicate 64b. It appears also that this comment was copied verbatim along with the rest of the multiplication code into ieee754dp_maddf, which has since been renamed _dp_maddf. Fix the same issue there. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13157/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add z argument macrosPaul Burton2016-05-135-9/+20
| | | | | | | | | | | | | Introduce macros for handling the "z" argument to maddf & msubf, making its handling consistent with that of the "x" & "y" arguments rather than open-coding equivalents. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13156/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Unify ieee754dp_m{add,sub}fPaul Burton2016-05-133-272/+21
| | | | | | | | | | | | | | | | The code for emulating MIPSr6 madd.d & msub.d instructions has previously been implemented as 2 different functions, namely ieee754dp_maddf & ieee754dp_msubf. The difference in behaviour of these 2 instructions is merely the sign of the product, so we can easily share the code implementing them. Do this for the double precision variant, removing the original ieee754dp_msubf in favor of reusing the code from ieee754dp_maddf. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13155/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Unify ieee754sp_m{add,sub}fPaul Burton2016-05-133-261/+21
| | | | | | | | | | | | | | | | The code for emulating MIPSr6 madd.s & msub.s instructions has previously been implemented as 2 different functions, namely ieee754sp_maddf & ieee754sp_msubf. The difference in behaviour of these 2 instructions is merely the sign of the product, so we can easily share the code implementing them. Do this for the single precision variant, removing the original ieee754sp_msubf in favor of reusing the code from ieee754sp_maddf. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Emulate MIPSr6 sel.fmt instructionPaul Burton2016-05-131-2/+24
| | | | | | | | | | | | | | | | Add support for emulating the MIPSr6 sel.fmt instruction, which was previously missing from the FPU emulation code. This instruction selects its result from 2 possible source registers, based upon bit 0 of the destination register, and is valid only for S (single) & D (double) data types. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13153/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: inst: Declare fsel_op for sel.fmt instructionPaul Burton2016-05-131-0/+1
| | | | | | | | | | | | | | Declare the opcode for the MIPSr6 sel.fmt instruction, as fsel_op in order to match other FP op names. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13152/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix BC1{EQ,NE}Z return offset calculationPaul Burton2016-05-131-15/+3
| | | | | | | | | | | | | | | The conditions for branching when emulating the BC1EQZ & BC1NEZ instructions were backwards, leading to each of those instructions being treated as the other. Fix this by reversing the conditions, and clear up the code a little for readability & checkpatch. Fixes: c8a34581ec09 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions") Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13151/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix BC1{EQ,NE}Z emulationPaul Burton2016-05-131-5/+6
| | | | | | | | | | | | | | | | The conditions for branching when emulating the BC1EQZ & BC1NEZ instructions were backwards, leading to each of those instructions being treated as the other. Fix this by reversing the conditions, and clear up the code a little for readability & checkpatch. Fixes: c909ca718e8f ("MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructions") Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13150/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support for extending builtin cmdlineRabin Vincent2016-05-132-0/+12
| | | | | | | | | | | | | | | | Allow the builtin command line to be extended by what the bootloader passes in. For example, the bootloader can pass specific arguments depending on the boot mode, and these should override the defaults in the builtin cmdline. The default MIPS_CMDLINE_FROM_BOOTLOADER option prepends the bootloader's cmdline to the builtin cmdline so is not suitable for this purpose. Signed-off-by: Rabin Vincent <rabinv@axis.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13181/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't add leading spacing to command linesRabin Vincent2016-05-131-2/+4
| | | | | | | | | The leading spaces don't affect functionality but are unnecessary. Signed-off-by: Rabin Vincent <rabinv@axis.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13180/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: genex: Indent delay slots & clean whitespaceJames Hogan2016-05-131-28/+28
| | | | | | | | | | | | | | Various branches and jumps in noreorder parts of genex.S don't have their delay slot instructions indented conventionally with the extra space. Fix these, as well as various other inconsistent whitespace problems in this file, such as spaces used after some opcodes instead of a tab. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13196/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support extended ASIDsPaul Burton2016-05-136-1/+58
| | | | | | | | | | | | | | | | | Add support for extended ASIDs as determined by the Config4.AE bit. Since the only supported CPUs known to implement this are Netlogic XLP and MIPS I6400, select this variable ASID support based upon CONFIG_CPU_XLP and CONFIG_CPU_MIPSR6. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Jayachandran C. <jchandra@broadcom.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13211/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Retrieve ASID masks using function accepting struct cpuinfo_mipsPaul Burton2016-05-1310-55/+86
| | | | | | | | | | | | | | | | | In preparation for supporting variable ASID masks, retrieve ASID masks using functions in asm/cpu-info.h which accept struct cpuinfo_mips. This will allow those functions to determine the ASID mask based upon the CPU in a later patch. This also allows for the r3k & r8k cases to be handled in Kconfig, which is arguably cleaner than the previous #ifdefs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13210/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: KVM/locore.S: Relax noatJames Hogan2016-05-131-11/+5
| | | | | | | | | | | | | | | | Now that the at register ($1) is no longer saved by __kvm_mips_vcpu_run(), relax the noat assembler directive so that it only applies around code where at is restored before entering guest, and saved after exiting guest. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13209/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: KVM/locore.S: Only preserve callee saved registersJames Hogan2016-05-131-47/+1
| | | | | | | | | | | | | | | Update __kvm_mips_vcpu_run() to only save and restore callee saved registers. It is always called using the standard ABIs, so the caller will preserve any other registers that need preserving. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13208/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: KVM: Abstract guest ASID maskPaul Burton2016-05-133-15/+18
| | | | | | | | | | | | | | | | | | In preparation for supporting varied widths of ASID mask in the kernel in general, switch KVM's guest ASIDs to a new KVM_ENTRYHI_ASID definition based on the 8-bit MIPS_ENTRYHI_ASID instead of ASID_MASK. It could potentially be used to support extended guest ASIDs in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13207/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add & use CP0_EntryHi ASID definitionsJames Hogan2016-05-134-4/+6
| | | | | | | | | | | | | | | | Add definitions for the ASID field in CP0_EntryHi (along with the soon to be used ASIDX field), and use them in a few previously hardcoded cases. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: KVM/locore.S: Don't preserve host ASID around vcpu_runJames Hogan2016-05-131-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS KVM uses different ASIDs for guest execution than for the host. The host ASID is saved on the stack when entering the guest with __kvm_mips_vcpu_run(), and restored again before returning back to the caller (exit to userland). - This does not take into account that pre-emption may have taken place during that time, which may have started a new ASID cycle and resulted in that process' ASID being invalidated and reused. - This does not take into account that the process may have migrated to a different CPU during that time, with a different ASID assignment since they are managed per-CPU. - It is actually redundant, since the host ASID will be restored correctly by kvm_arch_vcpu_put(), which is called almost immediately after kvm_arch_vcpu_ioctl_run() returns. Therefore drop this code from locore.S Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13206/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Change my email addressJohn Crispin2016-05-1356-58/+58
| | | | | | | | | The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MAINTAINERS: Change my email addressJohn Crispin2016-05-131-2/+2
| | | | | | | | | The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13200/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Implement __arch_bitrev* using bitswap for MIPSr6Paul Burton2016-05-132-0/+31
| | | | | | | | | | | | | | Release 6 of the MIPS architecture introduced the bitswap instruction, which reverses the bits within each byte of a word. Make use of this instruction to implement the __arch_bitrev* functions, which should be faster for most MIPSr6 CPUs, reduces code size slightly and allows us to avoid the lookup table used by the generic implementation, saving 256 bytes in the kernel binary by dropping that. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13204/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove no longer needed work_on_cpu() callAnna-Maria Gleixner2016-05-131-5/+7
| | | | | | | | | | | | | | | | | Since commit 3b9d6da67e11 ("cpu/hotplug: Fix rollback during error-out in __cpu_disable()") it is ensured that callbacks of CPU_ONLINE and CPU_DOWN_PREPARE are processed on the hotplugged CPU. Due to this work_on_cpu() calls are no longer required. Replace work_on_cpu() with a direct call of mips_cdmm_bus_up() or mips_cdmm_bus_down(). Description of those functions are adapted. Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: rt@linutronix.de Patchwork: https://patchwork.linux-mips.org/patch/13197/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: make PCI_DMA_BUS_IS_PHYS=1 constantSergey Ryazanov2016-05-135-20/+4
| | | | | | | | | | | No one of supported MIPS machines has an IOMMU unit, so we can safely define PCI_DMA_BUS_IS_PHYS = 1. Also remove iommu flag from the pci controller structure, since it is useless. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7604/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS64: Support of at least 48 bits of SEGBITSLeonid Yegoshin2016-05-133-8/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SEGBITS is 40 bits or more, depending on CPU type. Introduces optional support for 48 bits of application virtual address space. Only 16K and 64K pages are supported. Enabling will result in a memory overhead of a small number of pages for small applications. For 64K pages a 3rd level of page tables is required which has some impact during software TLB refill. [ralf@linux-mips.org: Fixed things raised in the review of the version posted and changed kconfig to be a bit more userfriendly.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: aleksey.makarov@auriga.com Cc: james.hogan@imgtec.com Cc: paul.burton@imgtec.com Cc: david.daney@cavium.com Cc: peterz@infradead.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: davidlohr@hp.com Cc: kirill@shutemov.name Cc: akpm@linux-foundation.org Cc: mingo@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10051/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS64: signal: Fix o32 sigaction syscallLeonid Yegoshin2016-05-132-4/+10
| | | | | | | | | | | | | | | | | MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly set to processing aka rt_sigaction() variant only. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: paul.burton@imgtec.com Cc: richard@nod.at Cc: luto@amacapital.net Cc: alex.smith@imgtec.com Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: mpe@ellerman.id.au Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: remove aliasing alignment if HW has antialising supportLeonid Yegoshin2016-05-131-1/+1
| | | | | | | | | | | | | | | | | | | MIPS hardware may have an antialising support and it works even page size is small. Setup a shared memory aliasing mask to page size if hardware has an antialising support. Big shared memory mask forces a disruption in page address assignment and that corrupts Android library memory handling. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: cernekee@gmail.com Cc: paul.gortmaker@windriver.com Cc: kumba@gentoo.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11516/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: traps: remove unused variableTony Wu2016-05-131-1/+0
| | | | | | | | | flags is indeed unused. Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENTHuacai Chen2016-05-137-8/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast TLB refill support, etc. This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to enable those enhancements which are not probed at run time. If you want a generic kernel to run on all Loongson 3 machines, please say 'N' here. If you want a high-performance kernel to run on new Loongson 3 machines only, please say 'Y' here. Some additional explanations: 1) SFB locates between core and L1 cache, it causes memory access out of order, so writel/outl (and other similar functions) need a I/O reorder barrier. 2) Loongson 3 has a bug that di instruction can not save the irqflag, so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di at all. 3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Fast TLB refill handlerHuacai Chen2016-05-139-5/+149
| | | | | | | | | | | | | | | | | Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which can be used for fast TLB refill. [ralf@linux-mips.org: Resolve conflict.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Invalidate special TLBs when neededHuacai Chen2016-05-133-12/+27
| | | | | | | | | | | | | | | | | | | Loongson-2 has a 4 entry itlb which is a subset of jtlb, Loongson-3 has a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. We should write diag register to invalidate itlb/dtlb when flushing jtlb because itlb/dtlb are not totally transparent to software. For Loongson-3A R2 (and newer), we should invalidate ITLB, DTLB, VTLB and FTLB before we enable/disable FTLB. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12753/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Set cache flush handlers to cache_noopHuacai Chen2016-05-131-0/+14
| | | | | | | | | | | | | | | | | | | Loongson-3 maintains cache coherency by hardware, this means: 1) It's icache is coherent with dcache. 2) It's dcaches don't alias (maybe depend on PAGE_SIZE). 3) It maintains cache coherency across cores (and for DMA). So we can skip most cache flush operations by setting relevant handlers to `cache_noop' in `r4k_cache_init'. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12752/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Add Loongson-3A R2 basic supportHuacai Chen2016-05-1315-32/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R2 revision of Loongson-3A: - Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache). - I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is 64 bytes. - 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way set-associative). - Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/ Execute-Inhibit. [ralf@linux-mips.org: Resolved merge conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12751/ Patchwork: https://patchwork.linux-mips.org/patch/13136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Adjust irq dispatch to speedup processingHuacai Chen2016-05-131-4/+6
| | | | | | | | | | | | | | This patch adjust the logic in mach_irq_dispatch(), allow multiple IPs handled in the same dispatching. This can speedup interrupt processing. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Move chipset ACPI code from drivers to archHuacai Chen2016-05-134-6/+1
| | | | | | | | | | | | | | SB700/SB710/SB800 chipset ACPI code is mostly Loongson-3 specific routines rather than a "platform driver". Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11273/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM1480: bcm1480_regs.h: strip redundant commentsAntonio Ospite2016-05-131-2/+2
| | | | | | | | | | Strip some comments which probably meant to repeat the same value of the define; they also contained a confusing 0x0x prefix. Signed-off-by: Antonio Ospite <ao2@ao2.it> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12254/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add and use watch register field definitionsJames Hogan2016-05-133-36/+63
| | | | | | | | | | | | | The files watch.c and ptrace.c contain various magic masks for WatchLo/WatchHi register fields. Add some definitions to mipsregs.h for these registers and make use of them in both watch.c and ptrace.c, hopefully making them more readable. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add and use CAUSEF_WP definitionJames Hogan2016-05-132-4/+3
| | | | | | | | | | | do_watch() clears bit 22 of cause without using a CAUSEF_* definition from mipsregs.h. Add a definition for this bit (CAUSEF_WP) and make use of it. Also use clear_c0_cause() instead of manual read/modify/write. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* watchdog: pic32-dmt: Add PIC32 deadman timer driverPurna Chandra Mandal2016-05-133-0/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for the deadman timer peripheral found on PIC32 class devices. The primary function of the deadman timer (DMT) is to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch timer, which is clocked whenever an instruction fetch occurs until a count match occurs. Instructions are not fetched when the processor is in sleep mode. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* dt/bindings: Add bindings for PIC32 deadman timer peripheralPurna Chandra Mandal2016-05-131-0/+19
| | | | | | | | | | | | | | | | | | | | | Document the devicetree bindings for the deadman timer peripheral found on Microchip PIC32 SoC class devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: Guenter Roeck <linux@roeck-us.net> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12702/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* watchdog: pic32-wdt: Add PIC32 watchdog driverJoshua Henderson2016-05-133-0/+277
| | | | | | | | | | | | | | | | | | | | | Add support for the watchdog peripheral found on PIC32 class devices. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* dt/bindings: Add bindings for PIC32 watchdog peripheralJoshua Henderson2016-05-131-0/+18
| | | | | | | | | | | | | | | | | | | | Document the devicetree bindings for the watchdog peripheral found on Microchip PIC32 SoC class devices. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: Guenter Roeck <linux@roeck-us.net> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: module: fix incorrect IS_ERR_VALUE macro usagesAndrzej Hajda2016-05-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | IS_ERR_VALUE macro should be used only with unsigned long type. Specifically it works incorrectly with longer types. The patch follows conclusion from discussion on LKML [1][2]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2120927 [2]: http://permalink.gmane.org/gmane.linux.kernel/2150581 [ralf@linux-mips.org: While it may not immediately be obvious, the type of st_value in the end is an unsigned long equivalent so the invocation of IS_ERR_VALUE() was valid but I'm applying the patch anyway for clarity.] Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12553/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Always propagate sNaN payload in quietingMaciej W. Rozycki2016-05-132-6/+12
| | | | | | | | | | | | | | | | | | | | | | | Propagate sNaN payload in quieting in the legacy-NaN mode as well. If clearing the quiet bit would produce infinity, then set the next lower trailing significand field bit, matching the SB-1 and BMIPS5000 hardware implementations. Some other MIPS FPU hardware implementations do produce the default qNaN bit pattern instead. This reverts some changes made for semantics preservation with commit dc3ddf42 [MIPS: math-emu: Update sNaN quieting handlers], consequently bringing back most of the semantics from before commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.], except from the qNaN produced in the infinity case. Previously the default qNaN bit pattern was produced in that case. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ELF: Restructure personality macrosMaciej W. Rozycki2016-05-131-7/+7
| | | | | | | | | | | | Update the ELF personality macros used for individual ABIs to make actions in the same order across all of them and match formatting too. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix uapi include in exported asm/siginfo.hJames Hogan2016-05-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | Since commit 8cb48fe169dd ("MIPS: Provide correct siginfo_t.si_stime"), MIPS' uapi/asm/siginfo.h has included uapi/asm-generic/siginfo.h directly before defining MIPS' struct siginfo, in order to get the necessary definitions needed for the siginfo struct without the generic copy_siginfo() hitting compiler errors due to struct siginfo not yet being defined. Now that the generic copy_siginfo() is moved out to linux/signal.h we can safely include asm-generic/siginfo.h before defining the MIPS specific struct siginfo, which avoids the uapi/ include as well as breakage due to generic copy_siginfo() being defined before struct siginfo. Reported-by: Christopher Ferris <cferris@google.com> Fixes: 8cb48fe169dd ("MIPS: Provide correct siginfo_t.si_stime") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Petr Malat <oss@malat.biz> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.0- Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* SIGNAL: Move generic copy_siginfo() to signal.hJames Hogan2016-05-132-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic copy_siginfo() is currently defined in asm-generic/siginfo.h, after including uapi/asm-generic/siginfo.h which defines the generic struct siginfo. However this makes it awkward for an architecture to use it if it has to define its own struct siginfo (e.g. MIPS and potentially IA64), since it means that asm-generic/siginfo.h can only be included after defining the arch-specific siginfo, which may be problematic if the arch-specific definition needs definitions from uapi/asm-generic/siginfo.h. It is possible to work around this by first including uapi/asm-generic/siginfo.h to get the constants before defining the arch-specific siginfo, and include asm-generic/siginfo.h after. However uapi headers can't be included by other uapi headers, so that first include has to be in an ifdef __kernel__, with the non __kernel__ case including the non-UAPI header instead. Instead of that mess, move the generic copy_siginfo() definition into linux/signal.h, which allows an arch-specific uapi/asm/siginfo.h to include asm-generic/siginfo.h and define the arch-specific siginfo, and for the generic copy_siginfo() to see that arch-specific definition. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Petr Malat <oss@malat.biz> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Christopher Ferris <cferris@google.com> Cc: linux-arch@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-ia64@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: <stable@vger.kernel.org> # 4.0- Patchwork: https://patchwork.linux-mips.org/patch/12478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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