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* arm64: pgalloc: consistently use PGALLOC_GFPMark Rutland2014-11-202-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently allocate different levels of page tables with a variety of differing flags, and the PGALLOC_GFP flags, intended for use when allocating any level of page table, are only used for ptes in pte_alloc_one. On x86, PGALLOC_GFP is used for all page table allocations. Currently the major differences are: * __GFP_NOTRACK -- Needed to ensure page tables are always accessible in the presence of kmemcheck to prevent recursive faults. Currently kmemcheck cannot be selected for arm64. * __GFP_REPEAT -- Causes the allocator to try to reclaim pages and retry upon a failure to allocate. * __GFP_ZERO -- Sometimes passed explicitly, sometimes zalloc variants are used. While we've no encountered issues so far, it would be preferable to be consistent. This patch ensures all levels of table are allocated in the same manner, with PGALLOC_GFP. Cc: Steve Capper <steve.capper@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64/mm: Remove hack in mmap randomize layoutYann Droneaud2014-11-181-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 8a0a9bd4db63 ('random: make get_random_int() more random'), get_random_int() returns a random value for each call, so comment and hack introduced in mmap_rnd() as part of commit 1d18c47c735e ('arm64: MMU fault handling and page table management') are incorrects. Commit 1d18c47c735e seems to use the same hack introduced by commit a5adc91a4b44 ('powerpc: Ensure random space between stack and mmaps'), latter copied in commit 5a0efea09f42 ('sparc64: Sharpen address space randomization calculations.'). But both architectures were cleaned up as part of commit fa8cbaaf5a68 ('powerpc+sparc64/mm: Remove hack in mmap randomize layout') as hack is no more needed since commit 8a0a9bd4db63. So the present patch removes the comment and the hack around get_random_int() on AArch64's mmap_rnd(). Cc: David S. Miller <davem@davemloft.net> Cc: Anton Blanchard <anton@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Dan McGee <dpmcgee@gmail.com> Signed-off-by: Yann Droneaud <ydroneaud@opteya.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: Add COMPAT_HWCAP_LPAECatalin Marinas2014-11-172-1/+3
| | | | | | | | | | | Commit a469abd0f868 (ARM: elf: add new hwcap for identifying atomic ldrd/strd instructions) introduces HWCAP_ELF for 32-bit ARM applications. As LPAE is always present on arm64, report the corresponding compat HWCAP to user space. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@vger.kernel.org> # 3.11+ Signed-off-by: Will Deacon <will.deacon@arm.com>
* mmu_gather: move minimal range calculations into generic codeWill Deacon2014-11-177-100/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | On architectures with hardware broadcasting of TLB invalidation messages , it makes sense to reduce the range of the mmu_gather structure when unmapping page ranges based on the dirty address information passed to tlb_remove_tlb_entry. arm64 already does this by directly manipulating the start/end fields of the gather structure, but this confuses the generic code which does not expect these fields to change and can end up calculating invalid, negative ranges when forcing a flush in zap_pte_range. This patch moves the minimal range calculation out of the arm64 code and into the generic implementation, simplifying zap_pte_range in the process (which no longer needs to care about start/end, since they will point to the appropriate ranges already). With the range being tracked by core code, the need_flush flag is dropped in favour of checking that the end of the range has actually been set. Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Cc: Michal Simek <monstr@monstr.eu> Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: entry: use ldp/stp instead of push/pop when saving/restoring regsWill Deacon2014-11-141-38/+37
| | | | | | | | | | | | | | | | | | The push/pop instructions can be suboptimal when saving/restoring large amounts of data to/from the stack, for example on entry/exit from the kernel. This is because: (1) They act on descending addresses (i.e. the newly decremented sp), which may defeat some hardware prefetchers (2) They introduce an implicit dependency between each instruction, as the sp has to be updated in order to resolve the address of the next access. This patch removes the push/pop instructions from our kernel entry/exit macros in favour of ldp/stp plus offset. Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: entry: avoid writing lr explicitly for constructing return pathsWill Deacon2014-11-141-20/+25
| | | | | | | | | | Using an explicit adr instruction to set the link register to point at ret_fast_syscall/ret_to_user can defeat branch and return stack predictors. Instead, use the standard calling instructions (bl, blr) and have an unconditional branch as the following instruction. Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: Fix up /proc/cpuinfoMark Rutland2014-11-141-24/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d7a49086f263164a (arm64: cpuinfo: print info for all CPUs) attempted to clean up /proc/cpuinfo, but due to concerns regarding further changes was reverted in commit 5e39977edf6500fd (Revert "arm64: cpuinfo: print info for all CPUs"). There are two major issues with the arm64 /proc/cpuinfo format currently: * The "Features" line describes (only) the 64-bit hwcaps, which is problematic for some 32-bit applications which attempt to parse it. As the same names are used for analogous ISA features (e.g. aes) despite these generally being architecturally unrelated, it is not possible to simply append the 64-bit and 32-bit hwcaps in a manner that might not be misleading to some applications. Various potential solutions have appeared in vendor kernels. Typically the format of the Features line varies depending on whether the task is 32-bit. * Information is only printed regarding a single CPU. This does not match the ARM format, and does not provide sufficient information in big.LITTLE systems where CPUs are heterogeneous. The CPU information printed is queried from the current CPU's registers, which is racy w.r.t. cross-cpu migration. This patch attempts to solve these issues. The following changes are made: * When a task with a LINUX32 personality attempts to read /proc/cpuinfo, the "Features" line contains the decoded 32-bit hwcaps, as with the arm port. Otherwise, the decoded 64-bit hwcaps are shown. This aligns with the behaviour of COMPAT_UTS_MACHINE and COMPAT_ELF_PLATFORM. In the absense of compat support, the Features line is empty. The set of hwcaps injected into a task's auxval are unaffected. * Properties are printed per-cpu, as with the ARM port. The per-cpu information is queried from pre-recorded cpu information (as used by the sanity checks). * As with the previous attempt at fixing up /proc/cpuinfo, the hardware field is removed. The only users so far are 32-bit applications tied to particular boards, so no portable applications should be affected, and this should prevent future tying to particular boards. The following differences remain: * No model_name is printed, as this cannot be queried from the hardware and cannot be provided in a stable fashion. Use of the CPU {implementor,variant,part,revision} fields is sufficient to identify a CPU and is portable across arm and arm64. * The following system-wide properties are not provided, as they are not possible to provide generally. Programs relying on these are already tied to particular (32-bit only) boards: - Hardware - Revision - Serial No software has yet been identified for which these remaining differences are problematic. Cc: Greg Hackmann <ghackmann@google.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Serban Constantinescu <serban.constantinescu@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: cross-distro@lists.linaro.org Cc: linux-api@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: kvm: eliminate literal pool entriesArd Biesheuvel2014-11-071-2/+2
| | | | | | | | | | Replace two instances of 'ldr xN, =(constant)' in the world switch hot path with 'mov' instructions. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: ftrace: eliminate literal pool entriesArd Biesheuvel2014-11-071-10/+11
| | | | | | | | Replace ldr xN, =<symbol> with adrp/add or adrp/ldr [as appropriate] in the implementation of _mcount(), which may be called very often. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: log physical ID of boot CPUMark Rutland2014-11-061-1/+4
| | | | | | | | | | | | | | | | | | In certain debugging scenarios it's useful to know the physical ID (i.e. the MPIDR_EL1.Aff* fields) of the boot CPU, but we don't currently log this as we do for 32-bit ARM kernels. This patch makes the kernel log the physical ID of the boot CPU early in the boot process. The CPU logical map initialisation is folded in to smp_setup_processor_id (which contrary to its name is also called by UP kernels). This is called before setup_arch, so should not adversely affect existing cpu_logical_map users. Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Lorenzo Pieralisis <lorenzo.pieralisi@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64/crypto: use crypto instructions to generate AES key scheduleArd Biesheuvel2014-11-065-11/+133
| | | | | | | | | | | | This patch implements the AES key schedule generation using ARMv8 Crypto Instructions. It replaces the table based C implementation in aes_generic.ko, which means we can drop the dependency on that module. Tested-by: Steve Capper <steve.capper@linaro.org> Acked-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64/kvm: Fix assembler compatibility of macrosGeoff Levand2014-11-061-10/+11
| | | | | | | | | | | | | | | | | Some of the macros defined in kvm_arm.h are useful in assembly files, but are not compatible with the assembler. Change any C language integer constant definitions using appended U, UL, or ULL to the UL() preprocessor macro. Also, add a preprocessor include of the asm/memory.h file which defines the UL() macro. Fixes build errors like these when using kvm_arm.h in assembly source files: Error: unexpected characters following instruction at operand 3 -- `and x0,x1,#((1U<<25)-1)' Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Geoff Levand <geoff@infradead.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64/dt: add machine name to kernel call stack dump outputArd Biesheuvel2014-11-061-0/+1
| | | | | | | | | | | | | | | | | | | This installs the machine name as recorded by setup_machine_fdt() as dump stack arch description. This results in the string to be included in call stack dumps, as is shown here: ... Bad mode in Synchronous Abort handler detected, code 0x84000005 CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.18.0-rc2+ #548 > Hardware name: linux,dummy-virt (DT) task: ffffffc07c870000 ti: ffffffc07c878000 task.ti: ffffffc07c878000 PC is at 0x0 ... Note that systems that support DMI/SMBIOS may override this later. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: xchg: Implement cmpxchg_doubleSteve Capper2014-11-062-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm64 architecture has the ability to exclusively load and store a pair of registers from an address (ldxp/stxp). Also the SLUB can take advantage of a cmpxchg_double implementation to avoid taking some locks. This patch provides an implementation of cmpxchg_double for 64-bit pairs, and activates the logic required for the SLUB to use these functions (HAVE_ALIGNED_STRUCT_PAGE and HAVE_CMPXCHG_DOUBLE). Also definitions of this_cpu_cmpxchg_8 and this_cpu_cmpxchg_double_8 are wired up to cmpxchg_local and cmpxchg_double_local (rather than the stock implementations that perform non-atomic operations with interrupts disabled) as they are used by the SLUB. On a Juno platform running on only the A57s I get quite a noticeable performance improvement with 5 runs of hackbench on v3.17: Baseline | With Patch -----------------+----------- Mean 119.2312 | 106.1782 StdDev 0.4919 | 0.4494 (times taken to complete `./hackbench 100 process 1000', in seconds) Signed-off-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: optimize memcpy_{from,to}io() and memset_io()Joonwoo Park2014-11-061-10/+56
| | | | | | | | | | | | | | Optimize memcpy_{from,to}io() and memset_io() by transferring in 64 bit as much as possible with minimized barrier usage. This simplest optimization brings faster throughput compare to current byte-by-byte read and write with barrier in the loop. Code's skeleton is taken from the powerpc. Link: http://lkml.kernel.org/p/20141020133304.GH23751@e104818-lin.cambridge.arm.com Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Trilok Soni <tsoni@codeaurora.org> Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: fix data type for physical addressMin-Hua Chen2014-11-061-1/+1
| | | | | | | | | Use phys_addr_t for physical address in alloc_init_pud. Although phys_addr_t and unsigned long are 64 bit in arm64, it is better to use phys_addr_t to describe physical addresses. Signed-off-by: Min-Hua Chen <orca.chen@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* Merge tag 'for-3.19' of git://git.linaro.org/people/ard.biesheuvel/linux-arm ↵Will Deacon2014-11-0511-29/+195
|\ | | | | | | | | | | | | | | | | | | | | | | into ard/efi-for-3.19 Pull UEFI updates from Ard Biesheuvel: - fixes for compliance with PE/COFF and UEFI specs - added support for SMBIOS, including upcoming version 3.0 - cleanups and diagnostic output improvements Signed-off-by: Will Deacon <will.deacon@arm.com>
| * efi: efi-stub: notify on DTB absenceMark Rutland2014-11-051-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the absence of a DTB configuration table, the EFI stub will happily continue attempting to boot a kernel, despite the fact that this kernel may not function without a description of the hardware. In this case, as with a typo'd "dtb=" option (e.g. "dbt=") or many other possible failures, the only output seen by the user will be the rather terse output from the EFI stub: EFI stub: Booting Linux Kernel... To aid those attempting to debug such failures, this patch adds a notice when no DTB is found, making the output more helpful: EFI stub: Booting Linux Kernel... EFI stub: Generating empty DTB Additionally, a positive acknowledgement is added when a user-specified DTB is in use: EFI stub: Booting Linux Kernel... EFI stub: Using DTB from command line Similarly, a positive acknowledgement is added when a DTB from a configuration table is in use: EFI stub: Booting Linux Kernel... EFI stub: Using DTB from configuration table Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Roy Franz <roy.franz@linaro.org> Acked-by: Matt Fleming <matt.fleming@intel.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * arm64: dmi: set DMI string as dump stack arch descriptionArd Biesheuvel2014-11-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | This sets the DMI string, containing system type, serial number, firmware version etc. as dump stack arch description, so that oopses and other kernel stack dumps automatically have this information included, if available. Tested-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * arm64: dmi: Add SMBIOS/DMI supportYi Li2014-11-053-0/+55
| | | | | | | | | | | | | | | | | | | | | | SMBIOS is important for server hardware vendors. It implements a spec for providing descriptive information about the platform. Things like serial numbers, physical layout of the ports, build configuration data, and the like. Signed-off-by: Yi Li <yi.li@linaro.org> Tested-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * dmi: add support for SMBIOS 3.0 64-bit entry pointArd Biesheuvel2014-11-051-7/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMTF SMBIOS reference spec v3.0.0 defines a new 64-bit entry point, which enables support for SMBIOS structure tables residing at a physical offset over 4 GB. This is especially important for upcoming arm64 platforms whose system RAM resides entirely above the 4 GB boundary. For the UEFI case, this code attempts to detect the new SMBIOS 3.0 header magic at the offset passed in the SMBIOS3_TABLE_GUID UEFI configuration table. If this configuration table is not provided, or if we fail to parse the header, we fall back to using the legacy SMBIOS_TABLE_GUID configuration table. This is in line with the spec, that allows both configuration tables to be provided, but mandates that they must point to the same structure table, unless the version pointed to by the 64-bit entry point is a superset of the 32-bit one. For the non-UEFI case, the detection logic is modified to look for the SMBIOS 3.0 header magic before it looks for the legacy header magic. Note that this patch is based on version 3.0.0d [draft] of the specification, which is expected not to deviate from the final version in ways that would affect the correctness of this implementation. Tested-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Acked-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Tony Luck <tony.luck@intel.com> Acked-by: Matt Fleming <matt.fleming@intel.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * efi: dmi: add support for SMBIOS 3.0 UEFI configuration tableArd Biesheuvel2014-11-053-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support to the UEFI side for detecting the presence of a SMBIOS 3.0 64-bit entry point. This allows the actual SMBIOS structure table to reside at a physical offset over 4 GB, which cannot be supported by the legacy SMBIOS 32-bit entry point. Since the firmware can legally provide both entry points, store the SMBIOS 3.0 entry point in a separate variable, and let the DMI decoding layer decide which one will be used. Tested-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Acked-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Matt Fleming <matt.fleming@intel.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * arm64/efi: drop redundant set_bit(EFI_CONFIG_TABLES)Ard Biesheuvel2014-11-051-2/+0
| | | | | | | | | | | | | | | | | | The EFI_CONFIG_TABLES bit already gets set by efi_config_init(), so there is no reason to set it again after this function returns successfully. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * arm64/efi: invert UEFI memory region reservation logicArd Biesheuvel2014-11-051-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of reserving the memory regions based on which types we know need to be reserved, consider only regions of the following types as free for general use by the OS: EFI_LOADER_CODE EFI_LOADER_DATA EFI_BOOT_SERVICES_CODE EFI_BOOT_SERVICES_DATA EFI_CONVENTIONAL_MEMORY Note that this also fixes a problem with the original code, which would misidentify a EFI_RUNTIME_SERVICES_DATA region as not reserved if it does not have the EFI_MEMORY_RUNTIME attribute set. However, it is perfectly legal for the firmware not to request a virtual mapping for EFI_RUNTIME_SERVICES_DATA regions that contain configuration tables, in which case the EFI_MEMORY_RUNTIME attribute would not be set. Acked-by: Roy Franz <roy.franz@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * arm64/efi: set PE/COFF file alignment to 512 bytesArd Biesheuvel2014-11-052-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | Change our PE/COFF header to use the minimum file alignment of 512 bytes (0x200), as mandated by the PE/COFF spec v8.3 Also update the linker script so that the Image file itself is also a round multiple of FileAlignment. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Roy Franz <roy.franz@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * arm64/efi: set PE/COFF section alignment to 4 KBArd Biesheuvel2014-11-051-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Position independent AArch64 code needs to be linked and loaded at the same relative offset from a 4 KB boundary, or adrp/add and adrp/ldr pairs will not work correctly. (This is how PC relative symbol references with a 4 GB reach are emitted) We need to declare this in the PE/COFF header, otherwise the PE/COFF loader may load the Image and invoke the stub at an offset which violates this rule. Reviewed-by: Roy Franz <roy.franz@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * arm64/efi: efistub: jump to 'stext' directly, not through the headerArd Biesheuvel2014-11-052-5/+8
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | After the EFI stub has done its business, it jumps into the kernel by branching to offset #0 of the loaded Image, which is where it expects to find the header containing a 'branch to stext' instruction. However, the UEFI spec 2.1.1 states the following regarding PE/COFF image loading: "A UEFI image is loaded into memory through the LoadImage() Boot Service. This service loads an image with a PE32+ format into memory. This PE32+ loader is required to load all sections of the PE32+ image into memory." In other words, it is /not/ required to load parts of the image that are not covered by a PE/COFF section, so it may not have loaded the header at the expected offset, as it is not covered by any PE/COFF section. So instead, jump to 'stext' directly, which is at the base of the PE/COFF .text section, by supplying a symbol 'stext_offset' to efi-entry.o which contains the relative offset of stext into the Image. Also replace other open coded calculations of the same value with a reference to 'stext_offset' Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Roy Franz <roy.franz@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* Linux 3.18-rc2v3.18-rc2Linus Torvalds2014-10-271-1/+1
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* Merge tag 'armsoc-for-rc2' of ↵Linus Torvalds2014-10-2618-46/+107
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "Another week, another small batch of fixes. Most of these make zynq, socfpga and sunxi platforms work a bit better: - due to new requirements for regulators, DWMMC on socfpga broke past v3.17 - SMP spinup fix for socfpga - a few DT fixes for zynq - another option (FIXED_REGULATOR) for sunxi is needed that used to be selected by other options but no longer is. - a couple of small DT fixes for at91 - ...and a couple for i.MX" * tag 'armsoc-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: dts: imx28-evk: Let i2c0 run at 100kHz ARM: i.MX6: Fix "emi" clock name typo ARM: multi_v7_defconfig: enable CONFIG_MMC_DW_ROCKCHIP ARM: sunxi_defconfig: enable CONFIG_REGULATOR_FIXED_VOLTAGE ARM: dts: socfpga: Add a 3.3V fixed regulator node ARM: dts: socfpga: Fix SD card detect ARM: dts: socfpga: rename gpio nodes ARM: at91/dt: sam9263: fix PLLB frequencies power: reset: at91-reset: fix power down register MAINTAINERS: add atmel ssc driver maintainer entry arm: socfpga: fix fetching cpu1start_addr for SMP ARM: zynq: DT: trivial: Fix mc node ARM: zynq: DT: Add cadence watchdog node ARM: zynq: DT: Add missing reference for memory-controller ARM: zynq: DT: Add missing reference for ADC ARM: zynq: DT: Add missing address for L2 pl310 ARM: zynq: DT: Remove 222 MHz OPP ARM: zynq: DT: Fix GEM register area size
| * Merge tag 'imx-fixes-3.18' of ↵Olof Johansson2014-10-263-12/+11
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes Merge "ARM: imx: fixes for 3.18" from Shawn Guo: The i.MX fixes for 3.18: - Revert one patch which increases I2C bus frequency on imx28-evk - Fix a typo on imx6q EIM clock name * tag 'imx-fixes-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx28-evk: Let i2c0 run at 100kHz ARM: i.MX6: Fix "emi" clock name typo Signed-off-by: Olof Johansson <olof@lixom.net>
| | * ARM: dts: imx28-evk: Let i2c0 run at 100kHzFabio Estevam2014-10-251-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 78b81f4666fb ("ARM: dts: imx28-evk: Run I2C0 at 400kHz") caused issues when doing the following sequence in loop: - Boot the kernel - Perform audio playback - Reboot the system via 'reboot' command In many times the audio card cannot be probed, which causes playback to fail. After restoring to the original i2c0 frequency of 100kHz there is no such problem anymore. This reverts commit 78b81f4666fbb22a20b1e63e5baf197ad2e90e88. Cc: <stable@vger.kernel.org> # 3.16+ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: i.MX6: Fix "emi" clock name typoSteve Longerbeam2014-10-252-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a typo error, the "emi" names refer to the eim clocks. The change fixes typo in EIM and EIM_SLOW pre-output dividers and selectors clock names. Notably EIM_SLOW clock itself is named correctly. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> [vladimir_zapolskiy@mentor.com: ported to v3.17] Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | Merge tag 'socfpga_fixes_for_3.18' of ↵Olof Johansson2014-10-249-23/+65
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.rocketboards.org/linux-socfpga-next into fixes Merge "SOCFPGA fixes for 3.18" from Dinh Nguyen: These patches fixes an SMP and SDMMC driver hang during boot up on the SOCFPGA platform. Patch "arm: socfpga: fix fetching cpu1start_addr for SMP" fixes the SMP trampoline code in order for CPU1 to correctly fetch it's cpu1start_addr. Patch "ARM: dts: socfpga: rename gpio nodes" renames that GPIO node in order to allow a standard way of specifying status="okay" in the board DTS file. Patch "ARM: dts: socfpga: Fix SD card detect" fixes a SDMMC driver hang during boot. The reason for the hang was the deferred probe of the SDMMC driver was waiting for the GPIO resource that would never come. Patch "ARM: dts: socfpga: Add a 3.3V fixed regulator node" adds a fixed regulator node for the SDMMC driver to use. * tag 'socfpga_fixes_for_3.18' of git://git.rocketboards.org/linux-socfpga-next: ARM: dts: socfpga: Add a 3.3V fixed regulator node ARM: dts: socfpga: Fix SD card detect ARM: dts: socfpga: rename gpio nodes arm: socfpga: fix fetching cpu1start_addr for SMP Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: dts: socfpga: Add a 3.3V fixed regulator nodeDinh Nguyen2014-10-234-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without the 3.3V regulator node, the SDMMC driver will give these warnings: dw_mmc ff704000.dwmmc0: No vmmc regulator found dw_mmc ff704000.dwmmc0: No vqmmc regulator found This patch adds the regulator node, and points the SD/MMC to the regulator. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Doug Anderson <dianders@chromium.org> --- v3: Rename nodes to have schematic-name_regulator and remove "boot-on" and "always-on" v2: Move the regulator nodes to their respective board dts file and correctly rename them to match the schematic
| | * | ARM: dts: socfpga: Fix SD card detectDinh Nguyen2014-10-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch, the booting the SOCFPGA platform would hang at the SDMMC driver loading. The issue, debugged by Doug Anderson, turned out to be that the GPIO bank used by the SD card-detect was not set to status="okay". Also update the cd-gpios to point to portb of the &gpio1 GPIO IP. Suggested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v4: Use &gpio1 to set status="okay" and update cd-gpio=&portb v3: Correctly degugged the issue to be a gpio node not having status="okay"
| | * | ARM: dts: socfpga: rename gpio nodesDinh Nguyen2014-10-231-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the Synopsys GPIO IP can support multiple ports of varying widths, it would make more sense to have the GPIO node DTS entry as this: gpio0: gpio@ff708000{ porta{ }; }; Also, this is documented in the snps-dwapb-gpio.txt. Suggested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| | * | arm: socfpga: fix fetching cpu1start_addr for SMPDinh Nguyen2014-10-214-15/+20
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CPU1 is brought out of reset, it's MMU is not turned on yet, so it will only be able to use physical addresses. For systems with that have the MMU page configured for 0xC0000000, 0x80000000, or 0x40000000 "BIC 0x40000000" will work just fine, as it was just converting the virtual address of &cpu1start_addr into a physical address, ie. 0xC0000000 became 0x80000000. So for systems where the SDRAM controller was able to do a wrap-around access, this was working fine, as it was just dropping the MSB, but for systems where out of bounds memory access is not allowed, this would not allow CPU1 to correctly fetch &cpu1start_addr. This patch fixes the secondary_trampoline code to correctly fetch the physical address of cpu1start_addr directly. The patch will subtract the correct PAGE_OFFSET from &cpu1start_addr. And since on this platform, the physical memory will always start at 0x0, subtracting PAGE_OFFSET from &cpu1start_addr will allow CPU1 to correctly fetch the value of cpu1start_addr. While at it, change the name of cpu1start_addr to socfpga_cpu1start_addr to avoid any future naming collisions for multiplatform image. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v4: Updated commit log to correctly lay out the usage of PAGE_OFFSET and add comments to the same effect. v3: Used PAGE_OFFSET to get the physical address v2: Correctly get the physical address instead of just a BIC hack.
| * | Merge tag 'at91-fixes' of ↵Olof Johansson2014-10-243-4/+12
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into fixes Merge "at91: fixes for v3.18 #1" from Nicholas Ferre: First AT91 fixes for 3.18: - one more MAINTAINERS entry for the SSC driver - a fix for the newly introduced power/reset driver - a fix on at91sam9263 USB due to PLLB misconfiguration * tag 'at91-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91/dt: sam9263: fix PLLB frequencies power: reset: at91-reset: fix power down register MAINTAINERS: add atmel ssc driver maintainer entry Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: at91/dt: sam9263: fix PLLB frequenciesBoris Brezillon2014-10-221-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PLLB input and output ranges were wrongly copied from at91sam9261 as the datasheet didn't mention explicitly PLLB. Correct their values. This fixes USB. Reported-by: Andreas Henriksson <andreas.henriksson@endian.se> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by: Andreas Henriksson <andreas.henriksson@endian.se> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | power: reset: at91-reset: fix power down registerAlexandre Belloni2014-10-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of at91sam9g45_restart(), the driver is writing AT91_DDRSDRC_LPCB_POWER_DOWN to AT91_DDRSDRC_RTR, this should actually be AT91_DDRSDRC_LPR. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Sebastian Reichel <sre@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | MAINTAINERS: add atmel ssc driver maintainer entryBo Shen2014-10-221-0/+7
| | |/ | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | Merge tag 'zynq-dt-fixes-for-3.18' of https://github.com/Xilinx/linux-xlnx ↵Olof Johansson2014-10-241-7/+17
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into fixes Merge "Xilinx Zynq dt fixes for v3.18" from Michal Simek: arm: Xilinx Zynq DT fixes for v3.18 - Fix gem register size - Fix OPP - Add missing references - Trivial cleanup * tag 'zynq-dt-fixes-for-3.18' of https://github.com/Xilinx/linux-xlnx: ARM: zynq: DT: trivial: Fix mc node ARM: zynq: DT: Add cadence watchdog node ARM: zynq: DT: Add missing reference for memory-controller ARM: zynq: DT: Add missing reference for ADC ARM: zynq: DT: Add missing address for L2 pl310 ARM: zynq: DT: Remove 222 MHz OPP ARM: zynq: DT: Fix GEM register area size Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: zynq: DT: trivial: Fix mc nodeMichal Simek2014-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | sed -i 's/}\ ;/};/g' Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | ARM: zynq: DT: Add cadence watchdog nodeMichal Simek2014-10-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add the cadence watchdog node to the Zynq devicetree. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | ARM: zynq: DT: Add missing reference for memory-controllerMichal Simek2014-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add missing reference for memory-controller. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | ARM: zynq: DT: Add missing reference for ADCMichal Simek2014-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add missing reference for ADC node. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | ARM: zynq: DT: Add missing address for L2 pl310Michal Simek2014-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By in sync with others node and add also baseaddr to the node name. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | ARM: zynq: DT: Remove 222 MHz OPPSoren Brinkmann2014-10-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to dependencies between timer and CPU frequency, only changes by powers of two are allowed. The clocksource driver prevents other changes, but with cpufreq and its governors it can result in being spammed with error messages constantly. Hence, remove the 222 MHz OPP. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | ARM: zynq: DT: Fix GEM register area sizeSoren Brinkmann2014-10-201-2/+2
| | |/ | | | | | | | | | | | | | | | | | | The size of the GEM's register area is only 0x1000 bytes. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: multi_v7_defconfig: enable CONFIG_MMC_DW_ROCKCHIPOlof Johansson2014-10-241-0/+1
| | | | | | | | | | | | | | | | | | | | | Allows booting from SD/MMC on RK3288 and other platforms. Added here so I can enable the board in the boot farm. Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-20 13:30:11 +0100