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* clk: sunxi: make clk-* explicitly non-modularPaul Gortmaker2016-07-076-65/+12
* clk: oxnas: make it explicitly non-modularPaul Gortmaker2016-07-071-12/+3
* clk: Kconfig: Name RK818 in Kconfig for COMMON_CLK_RK808Wadim Egorov2016-07-071-2/+2
* clk: hi6220: Change syspll and media_syspll clk to 1.19GHzXinliang Liu2016-07-071-2/+2
* clk: meson: make gxbb explicitly non-modularPaul Gortmaker2016-07-071-14/+4
* clk: meson8b: make it explicitly non-modularPaul Gortmaker2016-07-071-15/+4
* clk: qcom: add EBI2 clocks to the MSM8660 GCCLinus Walleij2016-07-021-0/+28
* clk: imx7d: only enable minimum required clocksDong Aisheng2016-07-021-8/+10
* clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLEDong Aisheng2016-07-021-357/+357
* clk: imx: add clk api for supporting CLK_OPS_PARENT_ENABLE clocksDong Aisheng2016-07-021-0/+32
* clk: imx: re-order and concentrate the same type of clk apiDong Aisheng2016-07-021-29/+29
* clk: core: support clocks which requires parents enable (part 2)Dong Aisheng2016-07-021-15/+33
* clk: core: support clocks which requires parents enable (part 1)Dong Aisheng2016-07-022-0/+7
* clk: move clk_disable_unused after clk_core_disable_unprepare functionDong Aisheng2016-07-021-98/+98
* clk: introduce clk_core_enable_lock and clk_core_disable_lock functionsDong Aisheng2016-07-021-22/+63
* Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/g...Stephen Boyd2016-07-023-52/+99
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| * clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bitsXing Zheng2016-07-011-1/+1
| * clk: rockchip: export rk3228 MAC clocksXing Zheng2016-07-011-11/+11
| * clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclkXing Zheng2016-07-011-3/+3
| * clk: rockchip: export rk3228 audio clocksXing Zheng2016-07-011-4/+4
| * Merge branch 'v4.8-shared/clkids' into v4.8-clk/nextHeiko Stuebner2016-07-011-0/+15
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| | * clk: rockchip: add clock-ids for rk3228 MAC clocksXing Zheng2016-06-221-0/+11
| | * clk: rockchip: add clock-ids for rk3228 audio clocksXing Zheng2016-06-221-0/+4
| * | clk: rockchip: include rk3228 downstream muxes into fractional dividersXing Zheng2016-07-011-29/+52
| * | clk: rockchip: fix incorrect rk3228 clock registersXing Zheng2016-06-221-9/+9
| * | clk: rockchip: add a dummy clock for the watchdog pclk on rk3399Xing Zheng2016-05-301-0/+9
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* | Merge tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd2016-07-029-667/+603
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| * | clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker2016-06-306-598/+531
| * | clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding2016-06-231-4/+4
| * | clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding2016-06-231-2/+2
| * | clk: tegra: Mark timer clock as criticalThierry Reding2016-06-221-1/+1
| * | clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding2016-06-172-1/+3
| * | clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding2016-06-172-12/+12
| * | clk: tegra: Disable spread spectrum on pll_d2Thierry Reding2016-06-171-2/+3
| * | clk: tegra: Fixup post dividers on Tegra210Thierry Reding2016-06-101-47/+47
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* | clk: fixed-factor: Allow for a few clocks to change the parent rateMaxime Ripard2016-07-022-1/+14
* | Merge tag 'imx-clk-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shaw...Stephen Boyd2016-06-306-49/+53
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| * | clk: imx6ul: fix gpt2 clock namesDong Aisheng2016-06-161-2/+2
| * | clk: imx: refine the powerdown bit of clk-pllv3Dong Aisheng2016-06-161-10/+10
| * | clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bitDong Aisheng2016-06-131-4/+4
| * | clk: imx: fix pll clock parentsDong Aisheng2016-06-125-34/+34
| * | clk: imx7d: correct dram pll typeAnson Huang2016-06-121-1/+1
| * | clk: imx7d: correct dram root clk parent selectAnson Huang2016-06-121-1/+1
| * | clk: imx: correct AV PLL rate formulaAnson Huang2016-06-121-2/+6
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* | Merge branch 'clk-hw-unregister-fixed-rate' into clk-nextStephen Boyd2016-06-302-0/+12
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| * | clk: fixed-rate: add clk_hw_unregister_fixed_rate()Masahiro Yamada2016-06-302-0/+12
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* | clk: hisilicon: hi3519: add driver remove path and fix some issuesJiancheng Xue2016-06-301-16/+100
* | clk: hisilicon: add hisi_clk_unregister_* functionsJiancheng Xue2016-06-301-0/+21
* | clk: hisilicon: add error processing for hisi_clk_register_* functionsJiancheng Xue2016-06-302-15/+55
* | clk: hisilicon: add hisi_clk_alloc function.Jiancheng Xue2016-06-302-0/+32
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