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* Merge tag 'dmaengine-4.12-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2017-05-1020-258/+304
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: "This time again a smaller update consisting of: - support for TI DA8xx dma controller and updates to the cppi driver - updates on bunch of drivers like xilinx, pl08x, stm32-dma, mv_xor, ioat, dmatest" * tag 'dmaengine-4.12-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (35 commits) dmaengine: pl08x: remove lock documentation dmaengine: pl08x: fix pl08x_dma_chan_state documentation dmaengine: pl08x: Use the BIT() macro consistently dmaengine: pl080: Fix some missing kerneldoc dmaengine: pl080: Cut some unused defines dmaengine: dmatest: Add check for supported buffer count (sg_buffers) dmaengine: dmatest: Select DMA_ENGINE_RAID as its needed for the slave_sg test dmaengine: virt-dma: Convert to use list_for_each_entry_safe() dma-debug: use offset_in_page() macro dmaengine: mv_xor: use offset_in_page() macro dmaengine: dmatest: use offset_in_page() macro dmaengine: sun4i: fix invalid argument dmaengine: ioat: use setup_timer dmaengine: cppi41: Fix an Oops happening in cppi41_dma_probe() dmaengine: pl330: remove pdata based initialization dmaengine: cppi: fix build error due to bad variable dmaengine: imx-sdma: add 1ms delay to ensure SDMA channel is stopped dmaengine: cppi41: use managed functions devm_*() dmaengine: cppi41: fix cppi41_dma_tx_status() logic dmaengine: qcom_hidma: pause the channel on shutdown ...
| * Merge branch 'topic/pl330' into for-linusVinod Koul2017-05-043-70/+8
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| | * dmaengine: pl330: remove pdata based initializationMarek Szyprowski2017-03-283-70/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is now used only on platforms which support device tree, so it is safe to remove legacy platform data based initialization code. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> For plat-samsung: Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/xilinx' into for-linusVinod Koul2017-05-041-28/+35
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| | * | dmaengine: xilinx: avoid memory corruption for device_prep_dma_memcpy()Akinobu Mita2017-03-141-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device_prep_dma_memcpy() callback for this driver allocates a new xilinx_dma_tx_descriptor whose TX segments list is initialized as empty, but then gets invalid TX segment pointer by list_last_entry() from the empty TX segments list and memory corruption happens by the attempt to update the next descriptor in invalid TX segment pointer. This removes unnecessary memory access for nonexistent tail TX segment which causes memory corruption. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: xilinx: fix device_terminate_all() callback for AXI CDMAAkinobu Mita2017-03-141-16/+33
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device_terminate_all() callback for this driver stops current DMA operations by clearing RUNSTOP bit in the control register and waiting HALTED bit set in the status register. But AXI CDMA which is one of the supported DMA engine by this driver does not provide the run / stop controls and those bits in the control and status registers are reserved. So when device_terminate_all() is called, the error message is printed and the channel is marked as having errors in xilinx_dma_halt(). This change adds stop_transfer() callback which differentiates CDMA and other DMA engine. The CDMA's one avoids the unsupported operations and instead polls the status register to check if the DMA operations are in progress for AXI CDMA. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/qcom' into for-linusVinod Koul2017-05-042-0/+21
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| | * | dmaengine: qcom_hidma: pause the channel on shutdownSinan Kaya2017-03-271-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ensure that all DMAs and interrupts are cleared during shutdown operation in order for kexec to start the next kernel clearly. Otherwise, HW could be performing a DMA into random addresses in the middle of second kernel start. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: qcom_hidma: disable/enable IRQs on pause/resumeSinan Kaya2017-03-271-0/+6
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Once the channels are stopped, disable interrupts to make sure no new HW interaction can happen. Similarly, re-enable the interrupts only if we know that channel is operational again. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/pl08x' into for-linusVinod Koul2017-05-042-38/+32
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| | * | dmaengine: pl08x: remove lock documentationVinod Koul2017-05-041-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | lock variable in pl08x_dma_chan_state no longer exists so remove it Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: pl08x: fix pl08x_dma_chan_state documentationVinod Koul2017-05-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Documentation for pl08x_dma_chan_state mentions it as struct whereas it is a enum, so fix that Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: pl08x: Use the BIT() macro consistentlyLinus Walleij2017-05-042-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the driver shift bits with BIT() which is used on other places in the driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: pl080: Fix some missing kerneldocLinus Walleij2017-05-041-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Two elements of the physical channel description was missing. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: pl080: Cut some unused definesLinus Walleij2017-05-041-9/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | There is no in-kernel code using these indexed register defines, and their offsets are clearly defined right below. Cut them. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/cppi' into for-linusVinod Koul2017-05-043-78/+137
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| | * | dmaengine: cppi41: Fix an Oops happening in cppi41_dma_probe()Alexandre Bailon2017-04-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fix an Oops happening on all platforms using the old dt bindings (all platforms but da8xx). This update cppi41_dma_probe() to use the index variable which is required to keep compatibility between old and new dt bindings. Fixes: 8e3ba95f4190 ("dmaengine: cppi41: use managed functions devm_*()") Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi: fix build error due to bad variableVinod Koul2017-03-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8e3ba95f4190 ("dmaengine: cppi41: use managed functions devm_*()") moved the code to devm_* but erranously changed a varible name, so fix it. drivers/dma/cppi41.c:1052:5: error: 'struct cppi41_dd' has no member named 'qmrg_mem' cdd->qmrg_mem = devm_ioremap_resource(dev, mem); ^ drivers/dma/cppi41.c:1053:16: error: 'struct cppi41_dd' has no member named 'qmrg_mem' if (IS_ERR(cdd->qmrg_mem)) ^ drivers/dma/cppi41.c:1054:21: error: 'struct cppi41_dd' has no member named 'qmrg_mem' return PTR_ERR(cdd->qmrg_mem); ^ Fixes: 8e3ba95f4190 ("dmaengine: cppi41: use managed functions devm_*()") Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: use managed functions devm_*()Andy Shevchenko2017-03-271-39/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the error handling much more simpler than open-coding everything and in addition makes the probe function smaller an tidier. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: fix cppi41_dma_tx_status() logicAndy Shevchenko2017-03-271-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It makes sense to set residue when channel is in progress. Otherwise it should be 0 since transfer is completed. Meanwhile this patch doesn't prevent to set residue value anyway. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: Fix teardown warningsAlexandre Bailon2017-03-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the teardown of a RX channel, because there is only one completion queue available for RX channel, descriptor of another channel may be popped which will cause 2 warnings: - the first one because we popped a wrong descriptor (neither the channel's descriptor, nor the teardown descriptor). - the second one happen during the teardown of another channel, because we can't find the channel descriptor (that is, the one that caused the first warning). To avoid that, use one free queue instead of a transmit completion queue. Note that fix doesn't fix all the teardown warnings: I still get some when I run some corner case. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: Add support of DA8xx to CPPI 4.1Alexandre Bailon2017-03-072-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DA8xx has a CPPI 4.1 DMA controller. This is add the glue layer required to make it work on DA8xx. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dt/bindings: da8xx-usb: Add binding for the CPPI 4.1 DMA controllerAlexandre Bailon2017-03-071-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DT binding for the TI DA8xx/OMAP-L1x/AM17xx/AM18xx CPPI 4.1 DMA controller. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: Remove isr callback from glue layerAlexandre Bailon2017-03-071-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the platform code to manage IRQ has been moved to MUSB, and now the interrupt handler is completely generic. Remove the isr callback that is not useful anymore. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: init_sched(): Get number of channels from DTAlexandre Bailon2017-03-071-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Despite the driver is already using DT to get the number of channels, init_sched() is using an hardcoded value to get it. Use DT to get the number of channels. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: Move some constants to glue layerAlexandre Bailon2017-03-071-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some constants are defined and use by the driver whereas they are specifics to AM335x. Add new variables to the glue layer, initialize them with the constants, and use them in the driver. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: rename platform variablesAlexandre Bailon2017-03-071-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, only the AM335x is supported by the driver. Though the driver has a glue layer to support different platforms, some platform variable names are not prefixed with the platform name. To facilitate the addition of a new platform, rename some variables owned by the AM335x glue. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: cppi41: Remove usbss_memAlexandre Bailon2017-03-071-8/+10
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make CPPI 4.1 DMA driver more generic, accesses to USBSS have been removed. So it is not required anymore to map the "glue" register's. Remove usbss_mem. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: dmatest: Add check for supported buffer count (sg_buffers)Stefan Roese2017-05-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using dmatest with sg_buffers=128 I stumbled upon the problem, that the "map_cnt" variable of "struct dmaengine_unmap_data" was set to 0. "map_cnt" is an "u8" variable, resulting in an overrun when its value is set to src_cnt + dst_cnt, to twice the sg_buffer value. This patch adds a small check to dmatest, so that this confusing error is detected and the test is aborted. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kedareswara rao Appana <appanad@xilinx.com> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: dmatest: Select DMA_ENGINE_RAID as its needed for the slave_sg testStefan Roese2017-05-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable usage of multiple SG buffers via the sg_buffers= module parameter, lets select DMA_ENGINE_RAID via Kconfig when DMATEST is configured. Otherwise the dmatest will "BUG" when more than 1 buffer (total of 2 for src + dst) is configured via sg_buffers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kedareswara rao Appana <appanad@xilinx.com> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: virt-dma: Convert to use list_for_each_entry_safe()Andy Shevchenko2017-04-261-6/+5
| | | | | | | | | | | | | | | | | | | | | Use list_for_each_entry_safe() instead of open coding variants. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dma-debug: use offset_in_page() macroGeliang Tang2017-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | | Use offset_in_page() macro instead of open-coding. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: mv_xor: use offset_in_page() macroGeliang Tang2017-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | | Use offset_in_page() macro instead of open-coding. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: dmatest: use offset_in_page() macroGeliang Tang2017-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | | Use offset_in_page() macro instead of open-coding. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: sun4i: fix invalid argumentMarc Gonzalez2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "pchans_used" field is an unsigned long array. for_each_clear_bit_from() expects an unsigned long pointer, not an array address. $ make C=2 drivers/dma/sun4i-dma.o CHECK drivers/dma/sun4i-dma.c drivers/dma/sun4i-dma.c:241:9: warning: incorrect type in argument 1 (different base types) drivers/dma/sun4i-dma.c:241:9: expected unsigned long const *p drivers/dma/sun4i-dma.c:241:9: got unsigned long ( *<noident> )[1] Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: ioat: use setup_timerGeliang Tang2017-04-241-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use setup_timer() instead of init_timer() to simplify the code. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: imx-sdma: add 1ms delay to ensure SDMA channel is stoppedJiada Wang2017-03-271-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sdma_disable_channel() cannot ensure dma is stopped to access module's FIFOs. There is chance SDMA core is running and accessing BD when disable of corresponding channel, this may cause sometimes even after call of .sdma_disable_channel(), SDMA core still be running and accessing module's FIFOs. According to NXP R&D team a delay of one BD SDMA cost time (maximum is 1ms) should be added after disable of the channel bit, to ensure SDMA core has really been stopped after SDMA clients call .device_terminate_all. This patch introduces adds a new function sdma_disable_channel_with_delay() which simply adds 1ms delay after call sdma_disable_channel(), and set it as .device_terminate_all. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: rcar-dmac: enable descriptor mode on 40bitKuninori Morimoto2017-03-271-20/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SYS-DMAC can use 40bit address transfer, and it supports Descriptor Mode too. Current SYS-DMAC driver disables Descriptor Mode if it was 40bit address today. But it can use Descriptor Mode with 40bit if transfer Source/Destination address are located in same 4GiB region in the 40 bit address space. This patch enables it if all condition was clear Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: imx-sdma: advertise correct residue granularityLucas Stach2017-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDMA hardware/driver does not actually report the transfer residue at burst size granularity, but in fact is only able to report residue after each finished segment. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: mv_xor: remove redundant null check on cdColin Ian King2017-03-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check to see if cd is null is redundant, pdata->channels is never null at this point, and hence &pdata->channels[i] cannot be null, so remove the null check. Detected by CoverityScan, CID#1357194 ("Logically Dead Code") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: stm32-dma: fix up error dev_err messageColin Ian King2017-03-061-1/+1
| |/ | | | | | | | | | | | | Trivial fix to spelling mistake and make channel plural. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Merge tag 'pwm/for-4.12-rc1' of ↵Linus Torvalds2017-05-1010-309/+685
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "Adds a new driver for the PWM controller found on MediaTek SoCs and extends support for the Atmel PWM controller to include the SAMA5D2. Some existing drivers have been migrated to the atomic API and a few others see miscellaneous improvements" * tag 'pwm/for-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: tegra: Read PWM clock source rate in driver init pwm: pca9685: Fix GPIO-only operation pwm: mediatek: Don't explicitly set .owner pwm: tegra: Avoid potential overflow for short periods pwm: tegra: Add support to configure pin state in suspends/resume pwm: tegra: Add DT binding details to configure pin in suspends/resume pwm: tegra: Increase precision in PWM rate calculation pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation pwm: Add MediaTek PWM support dt-bindings: pwm: Add MediaTek PWM bindings pwm: atmel: Enable PWM on sama5d2 pwm: atmel: Switch to atomic PWM pwm: atmel-hlcdc: Implement the suspend/resume hooks pwm: atmel-hlcdc: Convert to the atomic PWM API
| * \ Merge branch 'for-4.12/drivers' into for-nextThierry Reding2017-04-1310-309/+685
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| | * | pwm: tegra: Read PWM clock source rate in driver initLaxman Dewangan2017-04-131-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is required to know the PWM clock source frequency to calculate the PWM period. In driver, the clock source frequency of the PWM does not get change and, hence, get the clock source frequency in driver init. Get this values later for period calculation from pwm_config(). This will help in avoiding the clock call for getting clock rate in the pwm_config() each time. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * | pwm: pca9685: Fix GPIO-only operationSven Van Asbroeck2017-04-131-33/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO-only driver operation never clears the SLEEP bit, which can cause the GPIOs to become unusable. Example: 1. user requests first PWM -> driver clears SLEEP bit 2. user frees last PWM -> driver sets SLEEP bit 3. user requests GPIO 4. user switches GPIO on -> output does not turn on because SLEEP bit is set Prevent this behaviour by letting the runtime PM framework control the SLEEP bit. This will put the chip to SLEEP if no PWMs/GPIOs are exported or in use. Fixes: bccec89f0a35 ("Allow any of the 16 PWMs to be used as a GPIO") Reported-by: Sven Van Asbroeck <TheSven73@googlemail.com> Signed-off-by: Sven Van Asbroeck <TheSven73@googlemail.com> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * | pwm: mediatek: Don't explicitly set .ownerkbuild test robot2017-04-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/pwm/pwm-mediatek.c:210:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci CC: John Crispin <john@phrozen.org> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * | pwm: tegra: Avoid potential overflow for short periodsThierry Reding2017-04-131-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For very short periods, the result of the division might overflow the unsigned long hz variable (on 32-bit architectures). Avoid that by making it an unsigned long long. While at it, also remove an unneeded local variable whose only purpose is to store a temporary computation. Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * | pwm: tegra: Add support to configure pin state in suspends/resumeLaxman Dewangan2017-04-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. When system enters suspend, some PWM client/slave regulator devices require the PWM output to be tristated. Add support to configure the pin state via pinctrl frameworks in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * | pwm: tegra: Add DT binding details to configure pin in suspends/resumeLaxman Dewangan2017-04-121-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. When system enters suspend, some PWM client/slave regulator devices require the PWM output to be tristated. Add DT binding details to provide the pin configuration state from PWM and pinctrl DT node in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * | pwm: tegra: Increase precision in PWM rate calculationLaxman Dewangan2017-04-121-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rate of the PWM calculated as follows: hz = NSEC_PER_SEC / period_ns; rate = (rate + (hz / 2)) / hz; This has the precision loss in lower PWM rate. Change this to have more precision as: hz = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC * 100, period_ns); rate = DIV_ROUND_CLOSEST(rate * 100, hz) Example: 1. period_ns = 16672000, PWM clock rate is 200 KHz. Based on old formula hz = NSEC_PER_SEC / period_ns = 1000000000ul/16672000 = 59 (59.98) rate = (200K + 59/2)/59 = 3390 Based on new method: hz = 5998 rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334 If we measure the PWM signal rate, we will get more accurate period with rate value of 3334 instead of 3390. 2. period_ns = 16803898, PWM clock rate is 200 KHz. Based on old formula: hz = 59, rate = 3390 Based on new formula: hz = 5951, rate = 3360 The PWM signal rate of 3360 is more near to requested period than 3333. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-06 20:51:16 +0100