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* gpio: tz1090: Fix error handling of irq_of_parse_and_mapDmitry Torokhov2014-11-271-1/+1
| | | | | | | | | irq_of_parse_and_map() returns 0 on error, so testing for negative result never works. Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Acked-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tz1090-pinctrl.txt: Fix typo in bindingJames Hogan2014-11-271-1/+1
| | | | | | | | | Fix a typo, s/which which/which/ in the img,tz1090-pinctrl.txt binding. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinconf-generic: Declare dt_params/conf_items constSoren Brinkmann2014-11-111-3/+3
| | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'for_3.19/samsung-pinctrl' of ↵Linus Walleij2014-11-107-221/+435
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-pinctrl into devel Samsung pinctrl patches for v3.19 1) pinctrl-samsung data structure clean-up 8100cf4 pinctrl: samsung: Separate per-bank init and runtime data 1bf00d7 pinctrl: samsung: Constify samsung_pin_ctrl struct 94ce944 pinctrl: samsung: Constify samsung_pin_bank_type struct e06deff pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct 8799327 pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR() 2) pinctrl-samsung Exynos7 support 50cea0c pinctrl: exynos: Add initial driver data for Exynos7 14c255d pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts 6f5e41b pinctrl: exynos: Consolidate irq domain callbacks 0d3d30d pinctrl: exynos: Generalize the eint16_31 demux code 3) pinctrl-samsung Exynos4415 support 2891ba2 pinctrl: exynos: Add support for Exynos4415
| * pinctrl: exynos: Add support for Exynos4415Tomasz Figa2014-11-093-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin controllers of Exynos4415 are similar to Exynos4412, but certain differences cause the need to create separate driver data for it. This patch adds pin controller and bank descriptor arrays to the driver to support the new SoC. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> [cw00.choi: Rebase it on mainline kernel] Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> [tomasz.figa@gmail.com: Resolved merge with earlier clean-up series.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: exynos: Add initial driver data for Exynos7Naveen Krishna Ch2014-11-094-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial driver data for Exynos7 pinctrl support. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interruptsAbhilash Kesavan2014-11-093-10/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | Exynos7 uses different offsets for wakeup interrupt configuration registers. So a new irq_chip instance for Exynos7 wakeup interrupts is added. The irq_chip selection is now based on the wakeup interrupt controller compatible string. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: exynos: Consolidate irq domain callbacksAbhilash Kesavan2014-11-091-26/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding a irq_chip field to the samsung_pin_bank struct helps in consolidating the irq domain callbacks for external gpio and wakeup interrupt controllers. The exynos_wkup_irqd_ops and exynos_gpio_irqd_ops have now been merged into a single exynos_eint_irqd_ops. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: exynos: Generalize the eint16_31 demux codeAbhilash Kesavan2014-11-092-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external interrupt pending status and mask registers. So this function is not extensible for Exynos7 SoC which has these registers at different offsets. Generalize the exynos_irq_demux_eint16_31 function by using the pending/mask register offset values from the exynos_irq_chip structure. This is done by adding a irq_chip field to the samsung_pin_bank struct. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: samsung: Separate per-bank init and runtime dataTomasz Figa2014-11-095-33/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: samsung: Constify samsung_pin_ctrl structTomasz Figa2014-11-095-95/+97
| | | | | | | | | | | | | | | | | | | | In order to separate initialization constants from runtime data, this patch modifies the driver to store only constant data in samsung_pin_ctrl struct and copy data required at runtime to samsung_pinctrl_drv_data struct. This makes it possible to mark all existing instances of samsung_pin_ctrl struct as const and __initconst. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: samsung: Constify samsung_pin_bank_type structTomasz Figa2014-11-095-26/+24
| | | | | | | | | | | | | | | | This structure is not intended to be modified at runtime and functions as constant data shared between multiple pin banks. This patch makes all instances of it constant across the driver. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: samsung: Drop unused label field in samsung_pin_ctrl structTomasz Figa2014-11-094-30/+0
| | | | | | | | | | | | | | | | There is no code using it and in fact there are pin controller variants that do not even have this field initialized in their init data. This patch removes it completely. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()Tomasz Figa2014-11-091-3/+3
|/ | | | | | | | Currently the function returns a valid pointer on success and NULL on error, so exact error code is lost. This patch changes return convention of the function to use ERR_PTR() on error instead. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
* pinctrl: Add Intel Cherryview/Braswell pin controller supportMika Westerberg2014-11-043-0/+1532
| | | | | | | | | | | | This driver supports the pin/GPIO controllers found in newer Intel SoCs like Cherryview and Braswell. The driver provides full GPIO support and minimal set of pin controlling funtionality. The driver is based on the original Cherryview GPIO driver authored by Ning Li and Alan Cox. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()Mika Westerberg2014-11-041-3/+59
| | | | | | | | | | | | | | | | | | | | The GPIO resources (GpioIo/GpioInt) used in ACPI contain a GPIO number which is relative to the hardware GPIO controller. Typically this number can be translated directly to Linux GPIO number because the mapping is pretty much 1:1. However, when the GPIO driver is using pins exported by a pin controller driver via set of GPIO ranges, the mapping might not be 1:1 anymore and direct translation does not work. In such cases we need to translate the ACPI GPIO number to be suitable for the GPIO controller driver in question by checking all the pin controller GPIO ranges under the given device and using those to get the proper GPIO number. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Fix path error in documentationYingjoe Chen2014-11-041-1/+1
| | | | | | | Fix pinconfig include file path. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'v3.19-rockchip-pinctrl1' of ↵Linus Walleij2014-11-031-22/+94
|\ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into devel Rockchip-pinctrl fixes from Doug Anderson and suspend-specific functions from Chris Zhong
| * pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resumeChris Zhong2014-10-311-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | Save and restore the gpio6_c6 pinmux setting, since Maskrom of RK3288 would modify it to sdmmc0_det, so it need to be restored to the correct setting after resume from Maskrom. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * pinctrl: rockchip: add suspend/resume functionsChris Zhong2014-10-311-0/+18
| | | | | | | | | | | | | | | | | | | | | | support suspend/resume of pinctrl, it allows handling sleep mode for hogged pins in pinctrl Signed-off-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * pinctrl: rockchip: Protect read-modify-write with the spinlockDoug Anderson2014-10-291-0/+18
| | | | | | | | | | | | | | | | There were a few instances where the rockchip pinctrl driver would do read-modify-write with no spinlock. Add a spinlock for these cases. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * pinctrl: rockchip: Parse pin groups before calling pinctrl_register()Doug Anderson2014-10-291-6/+4
| | | | | | | | | | | | | | | | | | | | Just like in (529301c pinctrl: samsung: Parse pin groups before calling pinctrl_register()), Rockchip also needs to parse pin groups earlier to make hogs work. Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * pinctrl: rockchip: Don't call pinctrl_gpio_direction_output() in ↵Doug Anderson2014-10-291-16/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pin_config_set() The Rockchip pinctrl driver was calling rockchip_gpio_direction_output() in the pin_config_set() callback. This was just a shortcut for: * rockchip_gpio_set() * pinctrl_gpio_direction_output() Unfortunately it's not so good to call pinctrl_gpio_direction_output() from pin_config_set(). Specifically when initting hogs you'll get an error. Let's refactor a little so we can call _rockchip_pmx_gpio_set_direction() directly. Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * pinctrl: rockchip: Set wake_enabledDoug Anderson2014-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The rockchip pinctrl driver uses irq_gc_set_wake() but doesn't setup the .wake_enabled member. That means that we can never actually use a pin for wakeup. When "irq_set_irq_wake()" tries to call through it will always get a failure from set_irq_wake_real() and will then set wake_depth to 0. Assuming you can resume you'll later get an error message about "Unbalanced IRQ x wake disable". Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | pinctrl-bcm281xx: remove duplicate check on resourceVarka Bhadram2014-10-311-5/+0
| | | | | | | | | | | | | | Sanity check on resource happening with devm_ioremap_resource(). Signed-off-by: Varka Bhadram <varkab@cdac.in> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sunxi: Add A80 pinctrl muxing optionsMaxime Ripard2014-10-303-0/+754
| | | | | | | | | | | | | | | | | | The A80 has a rather usual pin controller, the only thing out of the ordinary being that it has 5 interrupts banks, and that some pins have several options for the same functions. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sunxi: Add PN bank base pinMaxime Ripard2014-10-301-0/+1
| | | | | | | | | | | | | | | | The A80 R-PIO controller has one more bank that what we've seen so far, add the PN pin bank. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mxs: warn if functions are not grouped by nameUwe Kleine-König2014-10-301-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mxs pinctrl driver cannot handle when functions are not grouped by name (which IMO is a bug). This happens for example if a imx28-somemachine.dts provides a function that has the same name as a function defined in imx28.dtsi. The proper way to fix that would be to check for duplicates in the loops (which increases parsing time) or parse the groups first and sort the resulting array. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | MAINTAINERS: Add entry for Intel pin controller driversMika Westerberg2014-10-291-0/+6
| | | | | | | | | | | | | | | | | | Add MAINTAINERS entry for Intel pin controller drivers. I will be maintaining them with Heikki, who kindly promised to help me with this. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Move Intel Baytrail pinctrl driver under intel directoryMika Westerberg2014-10-295-13/+20
| | | | | | | | | | | | | | | | We are going to have more pinctrl drivers for Intel hardware so separate all our pin controller drivers to own directory. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Qualcomm SPMI PMIC MPP pin controller driverIvan T. Ivanov2014-10-292-0/+950
| | | | | | | | | | | | | | | | | | This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm MPP sub-function blocks found in the PMIC chips. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Qualcomm SPMI PMIC GPIO pin controller driverIvan T. Ivanov2014-10-293-0/+947
| | | | | | | | | | | | | | | | | | This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm GPIO sub-function blocks found in the PMIC chips. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Device tree bindings for Qualcomm PMIC MPP blockIvan T. Ivanov2014-10-292-0/+206
| | | | | | | | | | | | | | | | | | DeviceTree binding documentation for Qualcomm SPMI PMIC MPP pinctrl drivers. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Device tree bindings for Qualcomm PMIC GPIO blockBjorn Andersson2014-10-292-0/+357
| | | | | | | | | | | | | | | | | | This introduced the device tree bindings for the GPIO block found in PMIC's from Qualcomm. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: at91: use own headerAlexandre Belloni2014-10-293-4/+74
| | | | | | | | | | | | | | | | | | | | Copy the mach/at91_pio.h header locally and use it for pinctrl-at91.c. This allows to remove the dependency on mach/at91_pio.h to be able to move at91 to multiplatform. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl-tb10x: remove duplicate check on resourceVarka Bhadram2014-10-281-6/+2
| | | | | | | | | | | | | | Sanity check on resource happening with devm_ioremap_resource(). Signed-off-by: Varka Bhadram <varkab@cdac.in> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: pinconf-generic: Add flag to print argumentsSoren Brinkmann2014-10-281-28/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | When dumping pinconf information in debugfs, config arguments are only printed when a unit is present and the argument is != 0. For parameters like the slew rate, this does not work. The slew rate uses a driver specific format for the argument, i.e. 0 can be a valid argument and a unit is not provided for it. For that reason, add a flag to enable printing the argument instead of inferring it from the presence of a unit and the value of the argument. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tegra-xusb: Don't leak configurationsThierry Reding2014-10-281-7/+12
| | | | | | | | | | | | | | | | | | The pinctrl config helpers make a separate copy of the configuration, so callers must make sure to free any dynamically allocated memory that was used to store it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: baytrail: add missing module removal supportFelipe Balbi2014-10-281-1/+6
| | | | | | | | | | | | | | | | | | | | | | pinctrl-baytrail driver provides a proper ->remove() method on its platform_driver definition, however there's no way, currently, to unload the driver due to missing module_exit(). This patch adds module_exit(). Signed-off-by: Felipe Balbi <balbi@ti.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: imx: add gpio pinmux support for vf610Stefan Agner2014-10-281-0/+72
| | | | | | | | | | | | | | | | | | | | Add pinmux support for GPIO for Vybrid (vf610) IOMUX controller. This is needed since direction configuration is not part of the GPIO module in Vybrid. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: st: Fix Sparse errorPramod Gurav2014-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This change fixes below sparse error, drivers/pinctrl/pinctrl-st.c:1515:31: error: incompatible types for operation (>) drivers/pinctrl/pinctrl-st.c:1515:31: left side has type void [noderef] <asn:2>*irqmux_base drivers/pinctrl/pinctrl-st.c:1515:31: right side has type int Cc: Maxime Coquelin <maxime.coquelin@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> CC: Linus Walleij <linus.walleij@linaro.org> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: amend MMC/SD pinsLinus Walleij2014-10-201-1/+3
| | | | | | | | | | | | | | There is a missing MMC/SD pin for MCDATDIR2 which is routed as alt B, add it to the MMC/SD pin group and functions. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: abx500: mark pin config as genericLinus Walleij2014-10-201-0/+1
| | | | | | | | | | | | This is generic pin configuration, so add .is_generic. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: abx500: update device tree bindingsLinus Walleij2014-10-201-109/+75
| | | | | | | | | | | | | | | | After force converting the ABx500 bindings in the driver and device tree sources, also update the binding documentation to state that we are now using standard bindings. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: abx500: retire phandle config mechanismLinus Walleij2014-10-201-13/+1
| | | | | | | | | | | | | | | | | | The abx500 pin control driver supported a method of fetching the generic config from a phandle to a separate node using the "ste,config" as a phandle. This is not used in any device trees and not documented in the bindings, so drop this support. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: abx500: force-convert to generic config bindingsLinus Walleij2014-10-203-44/+44
| | | | | | | | | | | | | | | | | | This converts the ABx500 pin controller and all associated device trees to use the standard, generic config bindings for pin controllers. There are no such device trees deployed in the wild so this is safe to do to set a good example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: force-convert to generic config bindingsLinus Walleij2014-10-2010-148/+148
| | | | | | | | | | | | | | | | | | This converts the Nomadik pin controller and all associated device trees to use the standard, generic config bindings for pin controllers. There are no such device trees deployed in the wild so this is safe to do to set a good example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: abx500: force-convert to generic mux bindingsLinus Walleij2014-10-203-90/+94
| | | | | | | | | | | | | | | | | | This converts the ABx500 pin controller and all associated device trees to use the standard, generic mux bindings for pin controllers. There are no such device trees deployed in the wild so this is safe to do to set a good example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: nomadik: force-convert to generic mux bindingsLinus Walleij2014-10-207-84/+88
|/ | | | | | | | | This converts the Nomadik pin controller and all associated device trees to use the standard, generic mux bindings for pin controllers. There are no such device trees deployed in the wild so this is safe to do to set a good example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Linux 3.18-rc1v3.18-rc1Linus Torvalds2014-10-201-2/+2
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