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* arm64: Remove pgprot_dmacoherent()Catalin Marinas2014-03-242-5/+1
| | | | | | | | | | Since this macro is identical to pgprot_writecombine() and is only used in a single place, remove it completely to avoid confusion. On ARMv7+ processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a. writecombine) to avoid mismatched hardware attribute aliases (with the kernel linear mapping as Normal Cacheable). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Support DMA_ATTR_WRITE_COMBINELaura Abbott2014-03-241-2/+12
| | | | | | | | DMA_ATTR_WRITE_COMBINE is currently ignored. Set the pgprot appropriately for non coherent opperations. Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Implement custom mmap functions for dma mappingLaura Abbott2014-03-241-0/+44
| | | | | | | | | | | | | | | | | | | The current dma_ops do not specify an mmap function so maping falls back to the default implementation. There are at least two issues with using the default implementation: 1) The pgprot is always pgprot_noncached (strongly ordered) memory even with coherent operations 2) dma_common_mmap calls virt_to_page on the remapped non-coherent address which leads to invalid memory being mapped. Fix both these issue by implementing a custom mmap function which correctly accounts for remapped addresses and sets vm_pg_prot appropriately. Signed-off-by: Laura Abbott <lauraa@codeaurora.org> [catalin.marinas@arm.com: replaced "arm64_" with "__" prefix for consistency] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Fix __range_ok macroChristopher Covington2014-03-201-2/+2
| | | | | | | | | | | | | | Without this, the following scenario is incorrectly determined to be invalid. addr 0x7f_ffffe000 size 8192 addr_limit 0x80_00000000 This behavior was observed while trying to vmsplice the stack as part of a CRIU dump of a process on a system started with the norandmaps kernel parameter. Signed-off-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Fix duplicated Kconfig entriesMark Brown2014-03-191-6/+0
| | | | | | | | | | | Probably due to rebasing over the lengthy time it took to get the patch merged commit addea9ef055b (cpufreq: enable ARM drivers on arm64) added a duplicate Power management options section. Add CPUfreq to the CPU power management section and remove a duplicate include of the main power section. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: mm: Route pmd thp functions through pte equivalentsSteve Capper2014-03-141-28/+24
| | | | | | | | | | | | | | | | Rather than have separate hugetlb and transparent huge page pmd manipulation functions, re-wire our thp functions to simply call the pte equivalents. This allows THP to take advantage of the new PTE_WRITE logic introduced in: c2c93e5 arm64: mm: Introduce PTE_WRITE To represent splitting THPs we use the PTE_SPECIAL bit as this is not used for pmds. Signed-off-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: rwsem: use asm-generic rwsem implementationWill Deacon2014-03-142-1/+2
| | | | | | | | | | | asm-generic offers an atomic-add based rwsem implementation, which can avoid the need for heavier, spinlock-based synchronisation on the fast path. This patch makes use of the optimised implementation for arm64 CPUs. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* asm-generic: rwsem: de-PPCify rwsem.hWill Deacon2014-03-141-5/+5
| | | | | | | | | | | | | | | asm-generic/rwsem.h used to live under arch/powerpc. During its liberation to common code, a few references to its former home where preserved, in particular the definition of RWSEM_ACTIVE_MASK is predicated on CONFIG_PPC64. This patch updates the ifdefs and comments to architecturally neutral versions. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Richard Kuo <rkuo@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: enable generic CPU feature modalias matching for this architectureArd Biesheuvel2014-03-142-0/+30
| | | | | | | | | | | | | This enables support for the generic CPU feature modalias implementation that wires up optional CPU features to udev based module autoprobing. A file <asm/cpufeature.h> is provided that maps CPU feature numbers to elf_hwcap bits, which is the standard way on arm64 to advertise optional CPU features both internally and to user space. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [catalin.marinas@arm.com: removed unnecessary "!!"] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: smp: make local symbol staticJingoo Han2014-03-131-1/+1
| | | | | | | | Make smp_spin_table_cpu_postboot() static, because this function is used only in this file. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: debug: make local symbols staticJingoo Han2014-03-131-2/+2
| | | | | | | | Make local symbols static, because these are used only in this file. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM64: perf: support dwarf unwinding in compat modeJean Pihet2014-03-132-2/+2
| | | | | | | | | | | | | | | | | | Add support for unwinding using the dwarf information in compat mode. Using the correct user stack pointer allows perf to record the frames correctly in the native and compat modes. Note that although the dwarf frame unwinding works ok using libunwind in native mode (on ARMv7 & ARMv8), some changes are required to the libunwind code for the compat mode. Those changes are posted separately on the libunwind mailing list. Tested on ARMv8 platform with v8 and compat v7 binaries, the latter are statically built. Signed-off-by: Jean Pihet <jean.pihet@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM64: perf: add support for frame pointer unwinding in compat modeJean Pihet2014-03-131-8/+67
| | | | | | | | | | When profiling a 32-bit application, user space callchain unwinding using the frame pointer is performed in compat mode. The code is taken over from the AARCH32 code and adapted to work on AARCH64. Signed-off-by: Jean Pihet <jean.pihet@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM64: perf: add support for perf registers APIJean Pihet2014-03-136-1/+90
| | | | | | | | | | | | | | | | | | | | | This patch implements the functions required for the perf registers API, allowing the perf tool to interface kernel register dumps with libunwind in order to provide userspace backtracing. Compat mode is also supported. Only the general purpose user space registers are exported, i.e.: PERF_REG_ARM_X0, ... PERF_REG_ARM_X28, PERF_REG_ARM_FP, PERF_REG_ARM_LR, PERF_REG_ARM_SP, PERF_REG_ARM_PC and not the PERF_REG_ARM_V* registers. Signed-off-by: Jean Pihet <jean.pihet@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Add boot time configuration of Intermediate Physical Address sizeRadha Mohan Chintakuntla2014-03-134-13/+21
| | | | | | | | | | | | | | ARMv8 supports a range of physical address bit sizes. The PARange bits from ID_AA64MMFR0_EL1 register are read during boot-time and the intermediate physical address size bits are written in the translation control registers (TCR_EL1 and VTCR_EL2). There is no change in the VA bits and levels of translation. Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Will Deacon <Will.deacon@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Do not synchronise I and D caches for special ptesCatalin Marinas2014-03-131-1/+1
| | | | | | | | | | | | Special pte mappings are not intended to be executable and do not even have an associated struct page. This patch ensures that we do not call __sync_icache_dcache() on such ptes. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Steve Capper <Steve.Capper@arm.com> Tested-by: Laura Abbott <lauraa@codeaurora.org> Tested-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Cc: <stable@vger.kernel.org>
* arm64: Make DMA coherent and strongly ordered mappings not executableCatalin Marinas2014-03-131-3/+3
| | | | | | | | | | | | pgprot_{dmacoherent,writecombine,noncached} don't need to generate executable mappings with side-effects like __sync_icache_dcache() being called when the mapping is in user space. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Tested-by: Laura Abbott <lauraa@codeaurora.org> Tested-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Cc: <stable@vger.kernel.org>
* arm64: barriers: add dmb barrierWill Deacon2014-03-101-0/+1
| | | | | | | | | | | Commit 8adbf57fc429 ("irqchip: gic: use dmb ishst instead of dsb when raising a softirq") added an explicit dmb(...) call to the GIC driver. This patch adds a simple dmb() macro to arm64, which expands to a DMB SY instruction. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: topology: Implement basic CPU topology supportMark Brown2014-03-045-1/+162
| | | | | | | | | | | | | | | | | | | | | | | | | Add basic CPU topology support to arm64, based on the existing pre-v8 code and some work done by Mark Hambleton. This patch does not implement any topology discovery support since that should be based on information from firmware, it merely implements the scaffolding for integration of topology support in the architecture. No locking of the topology data is done since it is only modified during CPU bringup with external serialisation from the SMP code. The goal is to separate the architecture hookup for providing topology information from the DT parsing in order to ease review and avoid blocking the architecture code (which will be built on by other work) with the DT code review by providing something simple and basic. Following patches will implement support for interpreting topology information from MPIDR and for parsing the DT topology bindings for ARM, similar patches will be needed for ACPI. Signed-off-by: Mark Brown <broonie@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> [catalin.marinas@arm.com: removed CONFIG_CPU_TOPOLOGY, always on if SMP] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: advertise ARMv8 extensions to 32-bit compat ELF binariesArd Biesheuvel2014-03-042-0/+38
| | | | | | | | | This adds support for advertising the presence of ARMv8 Crypto Extensions in the Aarch32 execution state to 32-bit ELF binaries running in 32-bit compat mode under the arm64 kernel. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: add AT_HWCAP2 support for 32-bit compatArd Biesheuvel2014-03-042-1/+3
| | | | | | | | Add support for the ELF auxv entry AT_HWCAP2 when running 32-bit ELF binaries in compat mode. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* binfmt_elf: add ELF_HWCAP2 to compat auxv entriesArd Biesheuvel2014-03-041-0/+5
| | | | | | | | | | Add ELF_HWCAP2 to the set of auxv entries that is passed to a 32-bit ELF program running in 32-bit compat mode under a 64-bit kernel. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: remove unnecessary cache flush at bootMark Rutland2014-03-042-7/+1
| | | | | | | | | | | | | | | | | | | | | | Currently we flush the entire dcache at boot within __cpu_setup, but this is unnecessary as the booting protocol demands that the dcache is invalid and off upon entering the kernel. The presence of the cache flush only serves to hide bugs in bootloaders, and is not safe in the presence of SMP. In an SMP boot scenario the CPUs enter coherency outside of the kernel, and the primary CPU enables its caches before bringing up secondary CPUs. Therefore if any secondary CPU has an entry in its cache (in violation of the boot protocol), the primary CPU might snoop it even if the secondary CPU's cache is disabled. The boot-time cache flush only serves to hide a firmware bug, and slows down a cpu boot unnecessarily. This patch removes the unnecessary boot-time cache flush. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> [catalin.marinas@arm.com: make __flush_dcache_all local only] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* cpufreq: enable ARM drivers on arm64Rob Herring2014-02-282-1/+9
| | | | | | | | | | | | Enable cpufreq and power kconfig menus on arm64 along with arm cpufreq drivers. The power menu is needed for OPP support. At least on Calxeda systems, the same cpufreq driver is used for arm and arm64 based systems. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: remove return value form psci_init()Vladimir Murzin2014-02-282-7/+4
| | | | | | | | | | psci_init() is written to return err code if something goes wrong. However, the single user, setup_arch(), doesn't care about it. Moreover, every error path is supplied with a clear message which is enough for pleasant debugging. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: remove redundant "psci:" prefixesVladimir Murzin2014-02-281-2/+2
| | | | | | | | | | Since 652af899799354049b273af897b798b8f03fdd88 "arm64: factor out spin-table boot method" psci prefix's been introduced. We have a common pr_fmt, so clean them up. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Implement coherent DMA API based on swiotlbCatalin Marinas2014-02-274-1/+253
| | | | | | | This patch adds support for DMA API cache maintenance on SoCs without hardware device cache coherency. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Use swiotlb late initialisationCatalin Marinas2014-02-272-4/+8
| | | | | | | | | | Since arm64 does not support ISA, there is no need for early swiotlb initialisation. This patch switches the DMA mapping code to swiotlb_tlb_late_init_with_default_size(). A side effect of this is that GFP_DMA is used for the swiotlb buffer and devices with a 32-bit coherent mask are correctly supported. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Replace ZONE_DMA32 with ZONE_DMACatalin Marinas2014-02-273-18/+19
| | | | | | | | On arm64 we do not have two DMA zones, so it does not make sense to implement ZONE_DMA32. This patch changes ZONE_DMA32 with ZONE_DMA, the latter covering 32-bit dma address space to honour GFP_DMA allocations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: vdso: clean up vdso_pagelist initializationNathan Lynch2014-02-261-30/+12
| | | | | | | | | | | | | | | | | | | Remove some unnecessary bits that were apparently carried over from another architecture's implementation: - No need to get_page() the vdso text/data - these are part of the kernel image. - No need for ClearPageReserved on the vdso text. - No need to vmap the first text page to check the ELF header - this can be done through &vdso_start. Also some minor cleanup: - Use kcalloc for vdso_pagelist array allocation. - Don't print on allocation failure, slab/slub will do that for us. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Change misleading function names in dma-mappingRitesh Harjani2014-02-261-10/+10
| | | | | | | | | | | | | arm64_swiotlb_alloc/free_coherent name can be misleading somtimes with CMA support being enabled after this patch (c2104debc235b745265b64d610237a6833fd53) Change this name to be more generic: __dma_alloc/free_coherent Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com> [catalin.marinas@arm.com: renamed arm64_swiotlb_dma_ops to coherent_swiotlb_dma_ops] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Fix the soft_restart routineGeoff Levand2014-02-261-1/+10
| | | | | | | | | | | | Change the soft_restart() routine to call cpu_reset() at its identity mapped physical address. The cpu_reset() routine must be called at its identity mapped physical address so that when the MMU is turned off the instruction pointer will be at the correct location in physical memory. Signed-off-by: Geoff Levand <geoff@infradead.org> for Huawei, Linaro Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Extend the idmap to the whole kernel imageCatalin Marinas2014-02-261-12/+8
| | | | | | | | | | | | This patch changes the idmap page table creation during boot to cover the whole kernel image, allowing functions like cpu_reset() to be safely called with the physical address. This patch also simplifies the create_block_map asm macro to no longer take an idmap argument and always use the phys/virt/end parameters. For the idmap case, phys == virt. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Convert asm/tlb.h to generic mmu_gatherCatalin Marinas2014-02-261-116/+20
| | | | | | | | | | | | | | | | | | Over the past couple of years, the generic mmu_gather gained range tracking - 597e1c3580b7 (mm/mmu_gather: enable tlb flush range in generic mmu_gather), 2b047252d087 (Fix TLB gather virtual address range invalidation corner cases) - and tlb_fast_mode() has been removed - 29eb77825cc7 (arch, mm: Remove tlb_fast_mode()). The new mmu_gather structure is now suitable for arm64 and this patch converts the arch asm/tlb.h to the generic code. One functional difference is the shift_arg_pages() case where previously the code was flushing the full mm (no tlb_start_vma call) but now it flushes the range given to tlb_gather_mmu() (possibly slightly more efficient previously). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Peter Zijlstra <peterz@infradead.org>
* arm64: Extend the PCI I/O space to 16MBCatalin Marinas2014-02-262-7/+11
| | | | | | | The patch moves the PCI I/O space (currently at 64K) before the earlyprintk mapping and extends it to 16MB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: enable processor debug state for secondary cpusVijaya Kumar K2014-02-262-4/+4
| | | | | | | | | | | | processor debug state PSTATE.D is unmasked in smp call clear_os_lock for secondary cpus. So debug state is still masked in normal kernel context. With this patch, unmask debug state on secondary boot for the cpus in normal kernel context. Now kgdb tests passed with multicore. Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: KGDB: Add KGDB configVijaya Kumar K2014-02-261-0/+1
| | | | | | | Add HAVE_ARCH_KGDB for arm64 Kconfig Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* misc: debug: remove compilation warningsVijaya Kumar K2014-02-261-1/+1
| | | | | | | | | | typecast instruction_pointer macro to unsigned long to resolve following compiler warnings like warning: format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'u64' [-Wformat] Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* KGDB: make kgdb_breakpoint() as noinlineVijaya Kumar K2014-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | The function kgdb_breakpoint() sets up break point at compile time by calling arch_kgdb_breakpoint(); Though this call is surrounded by wmb() barrier, the compile can still re-order the break point, because this scheduling barrier is not a code motion barrier in gcc. Making kgdb_breakpoint() as noinline solves this problem of code reording around break point instruction and also avoids problem of being called as inline function from other places More details about discussion on this can be found here http://comments.gmane.org/gmane.linux.ports.arm.kernel/269732 Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: KGDB: Add step debugging supportVijaya Kumar K2014-02-261-8/+56
| | | | | | | | | | | | | | | | Add KGDB software step debugging support for EL1 debug in AArch64 mode. KGDB registers step debug handler with debug monitor. On receiving 'step' command from GDB tool, target enables software step debugging and step address is updated in ELR. Software Step debugging is disabled when 'continue' command is received Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: KGDB: Add Basic KGDB supportVijaya Kumar K2014-02-264-0/+420
| | | | | | | | | | | Add KGDB debug support for kernel debugging. With this patch, basic KGDB debugging is possible.GDB register layout is updated and GDB tool can establish connection with target and can set/clear breakpoints. Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Add macros to manage processor debug stateVijaya Kumar K2014-02-263-17/+24
| | | | | | | | | | | | | Add macros to enable and disable to manage PSTATE.D for debugging. The macros local_dbg_save and local_dbg_restore are moved to irqflags.h file KGDB boot tests fail because of PSTATE.D is masked. unmask it for debugging support Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* Linux 3.14-rc4v3.14-rc4Linus Torvalds2014-02-241-1/+1
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* Merge tag 'fixes-for-linus' of ↵Linus Torvalds2014-02-2426-48/+108
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A collection of fixes for ARM platforms. Most are fixes for DTS files, mostly from DT conversion on OMAP which is still finding a few issues here and there. There's a couple of small stale code removal patches that we usually queue for the next release instead, but they seemed harmless enough to bring in now. Also, a fix for backlight on some PXA platforms, and a cache configuration fix for Tegra, etc" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits) MAINTAINERS: add additional ARM BCM281xx/BCM11xxx maintainer ARM: tegra: only run PL310 init on systems with one ARM: tegra: Add head numbers to display controllers ARM: imx6: build pm-imx6q.c independently of CONFIG_PM ARM: tegra: fix RTC0 alias for Cardhu ARM: dove: dt: revert PMU interrupt controller node Documentation: dt: OMAP: Update Overo/Tobi ARM: dts: Add support for both OMAP35xx and OMAP36xx Overo/Tobi ARM: dts: omap3-tobi: Use the correct vendor prefix ARM: dts: omap3-tobi: Fix boot with OMAP36xx-based Overo ARM: OMAP2+: Remove legacy macros for zoom platforms ARM: OMAP2+: Remove MACH_NOKIA_N800 ARM: dts: N900: add missing compatible property ARM: dts: N9/N950: fix boot hang with 3.14-rc1 ARM: OMAP1: nokia770: enable tahvo-usb ARM: OMAP2+: gpmc: fix: DT ONENAND child nodes not probed when MTD_ONENAND is built as module ARM: OMAP2+: gpmc: fix: DT NAND child nodes not probed when MTD_NAND is built as module ARM: dts: omap3-gta04: Fix mmc1 properties. ARM: dts: omap3-gta04: Fix 'aux' gpio key flags. ARM: OMAP2+: add missing ARCH_HAS_OPP ...
| * MAINTAINERS: add additional ARM BCM281xx/BCM11xxx maintainerMatt Porter2014-02-231-0/+1
| | | | | | | | | | | | | | | | | | Add myself as an additional maintainer for the Broadcom mobile SoCs. Signed-off-by: Matt Porter <mporter@linaro.org> Acked-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: only run PL310 init on systems with oneStephen Warren2014-02-191-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix tegra_init_cache() to check whether the system has a PL310 cache before touching the PL310 registers. This prevents access to non-existent registers on Tegra114 and later. Note for stable kernels: In <= v3.12, the file to patch is arch/arm/mach-tegra/common.c. Cc: <stable@vger.kernel.org> # v3.9+ Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: Add head numbers to display controllersThierry Reding2014-02-193-0/+12
| | | | | | | | | | | | | | | | | | | | The number of the head specifies the index of the display controller unit and is required to properly configure outputs so that they receive video data from the correct source. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * Merge tag 'mvebu-dt-fixes-3.14' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson2014-02-192-12/+2
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes mvebu dt fixes for v3.14 - mvebu: add missing 'eth3' alias for mv78260 - dove: revert PMU interrupt controller node, wait for driver to land. * tag 'mvebu-dt-fixes-3.14' of git://git.infradead.org/linux-mvebu: ARM: dove: dt: revert PMU interrupt controller node ARM: mvebu: dt: add missing alias 'eth3' on Armada XP mv78260 Signed-off-by: Olof Johansson <olof@lixom.net>
| | * ARM: dove: dt: revert PMU interrupt controller nodeJason Cooper2014-02-181-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The corresponding driver didn't make it into v3.14, so we need to remove the node. Dove systems fail to boot with the node present and no driver. This node will be re-added when the driver makes it to mainline. Reported-by: Jean-Francois Moine <moinejf@free.fr> Tested-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: mvebu: dt: add missing alias 'eth3' on Armada XP mv78260Willy Tarreau2014-02-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was correctly set on mv78460 but not on mv78260, resulting in my OpenBlocks AX3-4 retrieving only 3 of its 4 MAC addresses from the boot loader. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Willy Tarreau <w@1wt.eu> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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