summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'pinctrl-v5.9-1' of ↵Linus Torvalds2020-08-0986-1188/+7293
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of the pin control changes for the v5.9 kernel series: Core changes: - The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range() macro" was put in an immutable branch and merged into the pinctrl tree as well. We see these changes also here. - Improved debug output for pins used as GPIO. New drivers: - Ocelot Sparx5 SoC driver. - Intel Emmitsburg SoC subdriver. - Intel Tiger Lake-H SoC subdriver. - Qualcomm PM660 SoC subdriver. - Renesas SH-PFC R8A774E1 subdriver. Driver improvements: - Linear improvement and cleanups of the Intel drivers for Cherryview, Lynxpoint, Baytrail etc. Improved locking among other things. - Renesas SH-PFC has added support for RPC pins, groups, and functions to r8a77970 and r8a77980. - The newere Freescale (now NXP) i.MX8 pin controllers have been modularized. This is driven by the Google Android GKI initiative I think. - Open drain support for pins on the Qualcomm IPQ4019. - The Ingenic driver can handle both edges IRQ detection. - A big slew of documentation fixes all over the place. - A few irqchip template conversions by yours truly. * tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits) dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC pinctrl: stmfx: Use irqchip template pinctrl: amd: Use irqchip template pinctrl: mediatek: fix build for tristate changes pinctrl: samsung: Use bank name as irqchip name pinctrl: core: print gpio in pins debugfs file pinctrl: mediatek: add mt6779 eint support pinctrl: mediatek: add pinctrl support for MT6779 SoC pinctrl: mediatek: avoid virtual gpio trying to set reg pinctrl: mediatek: update pinmux definitions for mt6779 pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API pinctrl: mcp23s08: Use irqchip template pinctrl: sx150x: Use irqchip template dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes pinctrl: intel: Add Intel Emmitsburg pin controller support pinctl: ti: iodelay: Replace HTTP links with HTTPS ones Revert "gpio: omap: handle pin config bias flags" pinctrl: single: Use fallthrough pseudo-keyword pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword pinctrl: baytrail: Use fallthrough pseudo-keyword ...
| * dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoCAndy Teng2020-08-041-0/+202
| | | | | | | | | | | | | | | | | | | | Add devicetree bindings for MediaTek MT6779 pinctrl driver. Signed-off-by: Andy Teng <andy.teng@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1596115816-11758-2-git-send-email-hanks.chen@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stmfx: Use irqchip templateLinus Walleij2020-08-041-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | This makes the driver use the irqchip template to assign properties to the gpio_irq_chip instead of using the explicit calls to gpiochip_irqchip_add_nested() and gpiochip_set_nested_irqchip(). The irqchip is instead added while adding the gpiochip. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Amelie Delaunay <amelie.delaunay@st.com> Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Link: https://lore.kernel.org/r/20200721131814.357182-1-linus.walleij@linaro.org
| * pinctrl: amd: Use irqchip templateLinus Walleij2020-08-041-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | This makes the driver use the irqchip template to assign properties to the gpio_irq_chip instead of using the explicit call to gpiochip_irqchip_add(). The irqchip is instead added while adding the gpiochip. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Cc: Sandeep Singh <sandeep.singh@amd.com> Link: https://lore.kernel.org/r/20200722101545.144373-1-linus.walleij@linaro.org
| * pinctrl: mediatek: fix build for tristate changesRandy Dunlap2020-08-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export mtk_is_virt_gpio() for the case when CONFIG_PINCTRL_MTK=y CONFIG_PINCTRL_MTK_V2=y CONFIG_PINCTRL_MTK_MOORE=y CONFIG_PINCTRL_MTK_PARIS=m to fix this build error: ERROR: modpost: "mtk_is_virt_gpio" [drivers/pinctrl/mediatek/pinctrl-paris.ko] undefined! Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Sean Wang <sean.wang@kernel.org> Cc: linux-mediatek@lists.infradead.org Link: https://lore.kernel.org/r/d15827a3-d0c8-e231-9f61-8507b3d7be3a@infradead.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: samsung: Use bank name as irqchip nameMarek Szyprowski2020-08-041-26/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the bank name as the irqchip name. This name is later visible in /proc/interrupts, what makes it possible to easily identify each GPIO interrupt. /proc/interrupts before this patch: 143: 0 exynos4210_wkup_irq_chip 7 Edge hdmi 144: 0 exynos4210_wkup_irq_chip 6 Level wm8994 145: 1 exynos4210_wkup_irq_chip 7 Edge max77686-pmic, max77686-rtc 146: 1 exynos_gpio_irq_chip 3 Edge 3-0048 /proc/interrupts after this patch: 143: 0 gpx3 7 Edge hdmi 144: 0 gpx3 6 Level wm8994 145: 1 gpx0 7 Edge max77686-pmic, max77686-rtc 146: 1 gpm2 3 Edge 3-0048 Handling of the eint_wake_mask_value has been reworked, because each bank has now its own exynos_irq_chip structure allocated. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200720145412.24221-1-krzk@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: core: print gpio in pins debugfs fileDrew Fustini2020-08-041-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is a gpio range mapping for the pin, then print out the gpio chip and line index for the pin in the debugfs 'pins' file with the format: "[line-index]:[gpio-label]" Here is example output on the BeagleBoard.org PocketBeagle (AM3358): /sys/kernel/debug/pinctrl/44e10800.pinmux-pinctrl-single/pins pin 25 (PIN25) 25:gpio-32-63 44e10864 00000037 pinctrl-single pin 26 (PIN26) 26:gpio-32-63 44e10868 00000037 pinctrl-single pin 27 (PIN27) 27:gpio-32-63 44e1086c 00000037 pinctrl-single pin 28 (PIN28) 0:? 44e10870 00000036 pinctrl-single pin 29 (PIN29) 0:? 44e10874 00000006 pinctrl-single pin 30 (PIN30) 28:gpio-32-63 44e10878 00000027 pinctrl-single pin 31 (PIN31) 29:gpio-32-63 44e1087c 00000037 pinctrl-single pin 32 (PIN32) 30:gpio-32-63 44e10880 00000037 pinctrl-single pin 33 (PIN33) 31:gpio-32-63 44e10884 00000037 pinctrl-single pin 34 (PIN34) 0:gpio-64-95 44e10888 00000037 pinctrl-single pin 35 (PIN35) 1:gpio-64-95 44e1088c 00000037 pinctrl-single Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Suggested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Drew Fustini <drew@beagleboard.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20200722122751.266440-1-drew@beagleboard.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: add mt6779 eint supportHanks Chen2020-08-041-0/+8
| | | | | | | | | | | | | | | | | | | | add driver setting to support mt6779 eint Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/1595503197-15246-6-git-send-email-hanks.chen@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: add pinctrl support for MT6779 SoCHanks Chen2020-08-044-0/+2875
| | | | | | | | | | | | | | | | | | | | | | This adds MT6779 pinctrl driver based on MediaTek pinctrl-paris core. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Andy Teng <andy.teng@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/1595503197-15246-5-git-send-email-hanks.chen@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: avoid virtual gpio trying to set regHanks Chen2020-08-043-0/+33
| | | | | | | | | | | | | | | | | | | | | | for virtual gpios, they should not do reg setting and should behave as expected for eint function. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/1595503197-15246-4-git-send-email-hanks.chen@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: update pinmux definitions for mt6779Hanks Chen2020-07-231-0/+1242
| | | | | | | | | | | | | | | | | | | | | | Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Andy Teng <andy.teng@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Acked-by: Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/1595503197-15246-2-git-send-email-hanks.chen@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() APIFabien Dessenne2020-07-231-36/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the hwspin_lock_timeout_in_atomic() API which is the most appropriated here. Indeed: - hwspin_lock_() is called after spin_lock_irqsave() - the hwspin_lock_timeout() API relies on jiffies count which won't work if IRQs are disabled which is the case here. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Link: https://lore.kernel.org/r/20200615124456.27328-1-alexandre.torgue@st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mcp23s08: Use irqchip templateLinus Walleij2020-07-231-30/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the driver use the irqchip template to assign properties to the gpio_irq_chip instead of using the explicit calls to gpiochip_irqchip_add_nested() and gpiochip_set_nested_irqchip(). The irqchip is instead added while adding the gpiochip. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Jan Kundrát <jan.kundrat@cesnet.cz> Cc: Phil Reid <preid@electromag.com.au> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Jason Kridner <jkridner@gmail.com> Link: https://lore.kernel.org/r/20200721125223.344411-1-linus.walleij@linaro.org
| * pinctrl: sx150x: Use irqchip templateLinus Walleij2020-07-231-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the driver use the irqchip template to assign properties to the gpio_irq_chip instead of using the explicit calls to gpiochip_irqchip_add_nested() and gpiochip_set_nested_irqchip(). The irqchip is instead added while adding the gpiochip. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Cc: Peter Rosin <peda@axentia.se> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200721132537.362160-1-linus.walleij@linaro.org
| * Merge tag 'intel-pinctrl-v5.9-1' of ↵Linus Walleij2020-07-2210-329/+1191
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.9-1 * New driver for Emmitsburg * New driver for Tiger Lake-H * Part 3 of Cherryview driver clean up * Fix a glitch on Baytrail platforms The following is an automated git shortlog grouped by driver: ARM/orion/gpio: - Make use of for_each_requested_gpio() at91: - Make use of for_each_requested_gpio() baytrail: - Use fallthrough pseudo-keyword - Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) - Drop no-op ACPI_PTR() call cherryview: - Re-use data structures from pinctrl-intel.h (part 3) - Convert chv_writel() to use chv_padreg() - Introduce helpers to IO with common registers - Introduce chv_readl() helper gpio: - xra1403: Make use of for_each_requested_gpio() - mvebu: Make use of for_each_requested_gpio() gpiolib: - Introduce for_each_requested_gpio_in_range() macro intel: - Add Intel Emmitsburg pin controller support - Make use of for_each_requested_gpio_in_range() - Protect IO in few call backs by lock - Split intel_config_get() to three functions - Drop the only label in the code for consistency - Get rid of redundant 'else' in intel_config_set_debounce() - Make use of IRQ_RETVAL() - Reduce scope of the lock - Disable input and output buffer when switching to GPIO - Allow drivers to define ACPI address space ID - Allow drivers to define total amount of IRQs per community lynxpoint: - Drop no-op ACPI_PTR() call - Introduce helpers to enable or disable input - Make use of for_each_requested_gpio() merrifield: - Add I²S bus 2 pins to groups and functions - Update pin names in accordance with official list tigerlake: - Add support for Tiger Lake-H
| | * pinctrl: intel: Add Intel Emmitsburg pin controller supportAndy Shevchenko2020-07-213-0/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds pinctrl/GPIO support for Intel Emmitsburg PCH. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: baytrail: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-07-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * pinctrl: tigerlake: Add support for Tiger Lake-HMika Westerberg2020-06-291-0/+358
| | | | | | | | | | | | | | | | | | | | | | | | Intel Tiger Lake-H has different pin layout than the -LP variant so add support for this to the existing Tiger Lake driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * pinctrl: merrifield: Add I²S bus 2 pins to groups and functionsAndy Shevchenko2020-06-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to control I²S bus 2 pins if we would like to connect an audio codec. Reported-by: mouse <xllacyx@gmail.com> Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: merrifield: Update pin names in accordance with official listAndy Shevchenko2020-06-221-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | Some of the pin names were provided officially to the customers in different spelling. We update pin names in accordance with the official list. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., ↵Hans de Goede2020-06-221-14/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIOD_OUT_HIGH) The pins on the Bay Trail SoC have separate input-buffer and output-buffer enable bits and a read of the level bit of the value register will always return the value from the input-buffer. The BIOS of a device may configure a pin in output-only mode, only enabling the output buffer, and write 1 to the level bit to drive the pin high. This 1 written to the level bit will be stored inside the data-latch of the output buffer. But a subsequent read of the value register will return 0 for the level bit because the input-buffer is disabled. This causes a read-modify-write as done by byt_gpio_set_direction() to write 0 to the level bit, driving the pin low! Before this commit byt_gpio_direction_output() relied on pinctrl_gpio_direction_output() to set the direction, followed by a call to byt_gpio_set() to apply the selected value. This causes the pin to go low between the pinctrl_gpio_direction_output() and byt_gpio_set() calls. Change byt_gpio_direction_output() to directly make the register modifications itself instead. Replacing the 2 subsequent writes to the value register with a single write. Note that the pinctrl code does not keep track internally of the direction, so not going through pinctrl_gpio_direction_output() is not an issue. This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is already on at boot (no external monitor connected), then the i915 driver does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The temporarily going low of that GPIO was causing the panel to reset itself after which it would not show an image until it was turned off and back on again (until a full modeset was done on it). This commit fixes this. This commit also updates the byt_gpio_direction_input() to use direct register accesses instead of going through pinctrl_gpio_direction_input(), to keep it consistent with byt_gpio_direction_output(). Note for backporting, this commit depends on: commit e2b74419e5cc ("pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output") Cc: stable@vger.kernel.org Fixes: 86e3ef812fe3 ("pinctrl: baytrail: Update gpio chip operations") Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * pinctrl: baytrail: Drop no-op ACPI_PTR() callAndy Shevchenko2020-06-221-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Since we dependent on ACPI, there is no need to use ACPI_PTR() which is a no-op in this case. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: lynxpoint: Drop no-op ACPI_PTR() callAndy Shevchenko2020-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Since we dependent on ACPI, there is no need to use ACPI_PTR() which is a no-op in this case. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: lynxpoint: Introduce helpers to enable or disable inputAndy Shevchenko2020-06-221-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | Introduce couple of helpers to enable or disable input. i.e. lp_gpio_enable_input() and lp_gpio_disable_input(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: lynxpoint: Make use of for_each_requested_gpio()Andy Shevchenko2020-06-221-5/+6
| | | | | | | | | | | | | | | | | | | | | Make use of for_each_requested_gpio() instead of home grown analogue. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Make use of for_each_requested_gpio_in_range()Andy Shevchenko2020-06-221-15/+6
| | | | | | | | | | | | | | | | | | | | | Make use of for_each_requested_gpio_in_range() instead of home grown analogue. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Protect IO in few call backs by lockAndy Shevchenko2020-06-221-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Protect IO in intel_gpio_get_direction(), intel_gpio_community_irq_handler(), intel_config_get_debounce() and intel_config_get_pull() by lock. Even for simple readl() we better serialize IO to avoid potential problems. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Split intel_config_get() to three functionsAndy Shevchenko2020-06-221-28/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | Split intel_config_get() to three functions, i.e. intel_config_get() and two helpers intel_config_get_pull() and intel_config_get_debounce() to be symmetrical with intel_config_set*(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Drop the only label in the code for consistencyAndy Shevchenko2020-06-221-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the only label in the code, i.e. in intel_config_set_debounce(), for consistency with the rest. In entire driver we use multipoint return. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Get rid of redundant 'else' in intel_config_set_debounce()Andy Shevchenko2020-06-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a code like if (...) { ... goto label; } else { ... } the 'else' keyword is redundant. Get rid of it for better readability. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Make use of IRQ_RETVAL()Andy Shevchenko2020-06-221-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using bitwise operations against returned values, which is a bit fragile, convert IRQ handler to count amount of GPIO groups, where at least one interrupt happened, and convert it to returned value by IRQ_RETVAL() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Reduce scope of the lockAndy Shevchenko2020-06-221-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | In some cases lock covers unneeded calls and operations. Reduce scope of the lock in such cases. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Disable input and output buffer when switching to GPIOAndy Shevchenko2020-06-221-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's possible scenario that pin has been in different mode, while the respective GPIO register has a leftover output buffer enabled. In such case when we request GPIO it will switch to GPIO mode, and thus to output with unknown value, followed by switching to input mode. This can produce a glitch on the pin. Disable input and output buffer when switching to GPIO to avoid potential glitches. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: cherryview: Re-use data structures from pinctrl-intel.h (part 3)Andy Shevchenko2020-06-221-129/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have some data structures duplicated across the drivers. Let's deduplicate them by using struct intel_pinctrl_soc_data, struct intel_community and struct intel_pinctrl_context that are being provided by pinctrl-intel.h. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Allow drivers to define ACPI address space IDAndy Shevchenko2020-06-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Individual drivers may install ACPI OpRegion handlers based on address space ID which differs from community to community. Add special field in the struct intel_community for that purpose. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: intel: Allow drivers to define total amount of IRQs per communityAndy Shevchenko2020-06-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the pin control devices may not be capable to generate IRQ per each pin in the community. Allow individual drivers to define total amount of IRQs per community. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: cherryview: Convert chv_writel() to use chv_padreg()Andy Shevchenko2020-06-221-32/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chv_writel() is now solely used for cases where we write data to the PAD registers. In order to simplify callers, calculate register address inside chv_writel(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: cherryview: Introduce helpers to IO with common registersAndy Shevchenko2020-06-221-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Pin control device and effectively the single community in it has a set of common registers. It's good to have a helpers to IO on them. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * pinctrl: cherryview: Introduce chv_readl() helperAndy Shevchenko2020-06-221-35/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are plenty of places where we call readl(chv_padreg(pctrl, offset, ...)); Replace them with newly introduced chv_readl() helper chv_readl(pctrl, offset, ...); Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * | dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodesPaul Cercueil2020-07-211-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add YAML to describe the pinmux/pinconf sub-nodes of the pinctrl IP on Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200720154548.12453-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctl: ti: iodelay: Replace HTTP links with HTTPS onesAlexander A. Klimov2020-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Link: https://lore.kernel.org/r/20200718120807.19714-1-grandmaster@al2klimov.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Revert "gpio: omap: handle pin config bias flags"Linus Walleij2020-07-201-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 40e30d26d909af89de2dcd0b4abdd27c47ac2235. I applied the patch to the wrong tree, oooups. Also there is a new version of it. Revert it out of pinctrl and apply to the gpio tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: single: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20200716212317.GA17754@embeddedor Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-07-202-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20200716212213.GA17623@embeddedor Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: lpc18xx: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-07-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20200716212109.GA17525@embeddedor Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'sh-pfc-for-v5.9-tag2' of ↵Linus Walleij2020-07-179-514/+587
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.9 (take two) - Add support for the new RZ/G2H (R8A774E1) SoC, - One more conversion of DT bindings to json-schema, - Fix RZ/A1 kerneldoc.
| | * | dt-bindings: pinctrl: renesas,rza2-pinctrl: Convert to json-schemaGeert Uytterhoeven2020-07-162-87/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Renesas RZ/A2 combined Pin and GPIO controller Device Tree binding documentation to json-schema. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200626143638.16512-1-geert+renesas@glider.be
| | * | pinctrl: rza1: Demote some kerneldoc headers and fix othersLee Jones2020-07-161-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some description blocks are void of any description/documentation, others are missing 'struct' identifiers, there are also a couple of misspellings of function parameter names. Fix all of them. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/pinctrl-rza1.c:81: warning: cannot understand function prototype: 'struct rza1_bidir_pin ' drivers/pinctrl/pinctrl-rza1.c:90: warning: cannot understand function prototype: 'struct rza1_bidir_entry ' drivers/pinctrl/pinctrl-rza1.c:98: warning: cannot understand function prototype: 'struct rza1_swio_pin ' drivers/pinctrl/pinctrl-rza1.c:108: warning: cannot understand function prototype: 'struct rza1_swio_entry ' drivers/pinctrl/pinctrl-rza1.c:116: warning: cannot understand function prototype: 'struct rza1_pinmux_conf ' drivers/pinctrl/pinctrl-rza1.c:443: warning: cannot understand function prototype: 'struct rza1_mux_conf ' drivers/pinctrl/pinctrl-rza1.c:462: warning: cannot understand function prototype: 'struct rza1_port ' drivers/pinctrl/pinctrl-rza1.c:482: warning: cannot understand function prototype: 'struct rza1_pinctrl ' drivers/pinctrl/pinctrl-rza1.c:546: warning: Function parameter or member 'port' not described in 'rza1_pinmux_get_flags' drivers/pinctrl/pinctrl-rza1.c:546: warning: Function parameter or member 'pin' not described in 'rza1_pinmux_get_flags' drivers/pinctrl/pinctrl-rza1.c:546: warning: Function parameter or member 'func' not described in 'rza1_pinmux_get_flags' drivers/pinctrl/pinctrl-rza1.c:546: warning: Function parameter or member 'rza1_pctl' not described in 'rza1_pinmux_get_flags' drivers/pinctrl/pinctrl-rza1.c:575: warning: Function parameter or member 'port' not described in 'rza1_set_bit' drivers/pinctrl/pinctrl-rza1.c:575: warning: Function parameter or member 'reg' not described in 'rza1_set_bit' drivers/pinctrl/pinctrl-rza1.c:575: warning: Function parameter or member 'bit' not described in 'rza1_set_bit' drivers/pinctrl/pinctrl-rza1.c:575: warning: Function parameter or member 'set' not described in 'rza1_set_bit' drivers/pinctrl/pinctrl-rza1.c:672: warning: Function parameter or member 'rza1_pctl' not described in 'rza1_pin_mux_single' drivers/pinctrl/pinctrl-rza1.c:672: warning: Excess function parameter 'pinctrl' description in 'rza1_pin_mux_single' Signed-off-by: Lee Jones <lee.jones@linaro.org> Acked-by: Jacopo Mondi <jacopo@jmondi.org> Link: https://lore.kernel.org/r/20200713144930.1034632-21-lee.jones@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: sh-pfc: pfc-r8a77951: Add R8A774E1 PFC supportLad Prabhakar2020-07-145-415/+474
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (R8A77951), however it doesn't have several automotive specific peripherals. Add automotive-specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594138692-16816-13-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | dt-bindings: pinctrl: sh-pfc: Document r8a774e1 PFC supportMarian-Cristian Rotariu2020-07-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document PFC support for the RZ/G2H (R8A774E1) SoC. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594138692-16816-12-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 04:41:57 +0100