| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | vhost: generalize adding used elem | Jason Wang | 2019-06-05 | 1 | -10/+1 | |
| * | | | | Merge tag 'vfio-v5.3-rc1' of git://github.com/awilliam/linux-vfio | Linus Torvalds | 2019-07-17 | 4 | -28/+34 | |
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| | * | | | | mdev: Send uevents around parent device registration | Alex Williamson | 2019-07-11 | 1 | -0/+9 | |
| | * | | | | sample/mdev/mbochs: remove set but not used variable 'mdev_state' | YueHaibing | 2019-07-02 | 1 | -3/+0 | |
| | * | | | | vfio: vfio_pci_nvlink2: use a vma helper function | Peng Hao | 2019-07-02 | 1 | -2/+1 | |
| | * | | | | vfio-mdev/samples: make some symbols static | Kefeng Wang | 2019-07-02 | 1 | -23/+24 | |
| * | | | | | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2019-07-17 | 148 | -3216/+7732 | |
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| | *-----. \ \ \ \ | Merge branches 'clk-bcm63xx', 'clk-silabs', 'clk-lochnagar' and 'clk-rockchip... | Stephen Boyd | 2019-07-12 | 21 | -175/+1997 | |
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| | | | | | * \ \ \ \ | Merge tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/g... | Stephen Boyd | 2019-07-12 | 10 | -46/+29 | |
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| | | | | | | * | | | | clk: rockchip: export HDMIPHY clock on rk3228 | Heiko Stuebner | 2019-06-27 | 1 | -1/+1 | |
| | | | | | | * | | | | clk: rockchip: add watchdog pclk on rk3328 | Heiko Stuebner | 2019-06-27 | 1 | -0/+3 | |
| | | | | | | * | | | | Merge branch 'v5.3-shared/clk-ids' into v5.3-clk/next | Heiko Stuebner | 2019-06-27 | 2 | -0/+2 | |
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| | | | | | | | * | | | | clk: rockchip: add clock id for hdmi_phy special clock on rk3228 | Heiko Stuebner | 2019-06-27 | 1 | -0/+1 | |
| | | | | | | | * | | | | clk: rockchip: add clock id for watchdog pclk on rk3328 | Heiko Stuebner | 2019-06-27 | 1 | -0/+1 | |
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| | | | | | | * | | | | clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro | Heiko Stuebner | 2019-06-15 | 4 | -36/+12 | |
| | | | | | | * | | | | clk: rockchip: add a type from SGRF-controlled gate clocks | Heiko Stuebner | 2019-06-14 | 1 | -0/+4 | |
| | | | | | | * | | | | clk: rockchip: Remove 48 MHz PLL rate from rk3288 | Douglas Anderson | 2019-06-06 | 1 | -1/+0 | |
| | | | | | | * | | | | clk: rockchip: add 1.464GHz cpu-clock rate to rk3228 | Justin Swartz | 2019-05-20 | 1 | -0/+1 | |
| | | | | | | * | | | | clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase() | Douglas Anderson | 2019-05-20 | 1 | -3/+3 | |
| | | | | | | * | | | | clk: rockchip: Don't yell about bad mmc phases when getting | Douglas Anderson | 2019-05-20 | 1 | -3/+1 | |
| | | | | | | * | | | | clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation | Douglas Anderson | 2019-05-20 | 1 | -2/+2 | |
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| | | | | * | | | | | clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK | Charles Keepax | 2019-06-27 | 1 | -0/+1 | |
| | | | | * | | | | | clk: lochnagar: Use new parent_data approach to register clock parents | Charles Keepax | 2019-06-26 | 1 | -119/+86 | |
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| | | | * | | | | | clk: Add Si5341/Si5340 driver | Mike Looijmans | 2019-06-27 | 3 | -0/+1358 | |
| | | | * | | | | | dt-bindings: clock: Add silabs,si5341 | Mike Looijmans | 2019-06-27 | 1 | -0/+162 | |
| | | | * | | | | | clk: clk-si544: Implement small frequency change support | Mike Looijmans | 2019-06-27 | 1 | -10/+92 | |
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| | | * | | | | | clk: add BCM63XX gated clock controller driver | Jonas Gorski | 2019-06-27 | 3 | -0/+247 | |
| | | * | | | | | devicetree: document the BCM63XX gated clock bindings | Jonas Gorski | 2019-06-27 | 1 | -0/+22 | |
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| | *-------. \ \ \ \ | Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h', 'cl... | Stephen Boyd | 2019-07-12 | 19 | -116/+592 | |
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| | | | | | | * | | | | | clk: at91: sckc: use dedicated functions to unregister clock | Claudiu Beznea | 2019-06-27 | 1 | -2/+2 | |
| | | | | | | * | | | | | clk: at91: sckc: improve error path for sama5d4 sck registration | Claudiu Beznea | 2019-06-27 | 1 | -15/+28 | |
| | | | | | | * | | | | | clk: at91: sckc: remove unnecessary line | Claudiu Beznea | 2019-06-27 | 1 | -1/+0 | |
| | | | | | | * | | | | | clk: at91: sckc: improve error path for sam9x5 sck register | Claudiu Beznea | 2019-06-27 | 1 | -18/+32 | |
| | | | | | | * | | | | | clk: at91: sckc: add support to free slow clock osclillator | Claudiu Beznea | 2019-06-27 | 1 | -0/+8 | |
| | | | | | | * | | | | | clk: at91: sckc: add support to free slow rc oscillator | Claudiu Beznea | 2019-06-27 | 1 | -0/+8 | |
| | | | | | | * | | | | | clk: at91: sckc: add support to free slow oscillator | Claudiu Beznea | 2019-06-27 | 1 | -0/+8 | |
| | | | | | | * | | | | | clk: at91: sckc: add support for SAM9X60 | Claudiu Beznea | 2019-06-26 | 1 | -0/+74 | |
| | | | | | | * | | | | | dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller | Claudiu Beznea | 2019-06-26 | 1 | -3/+4 | |
| | | | | | | * | | | | | clk: at91: sckc: add support to specify registers bit offsets | Claudiu Beznea | 2019-06-26 | 1 | -32/+61 | |
| | | | | | | * | | | | | clk: at91: sckc: sama5d4 has no bypass support | Claudiu Beznea | 2019-06-26 | 1 | -6/+0 | |
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| | | | | | * | | | | | clk: sprd: Add check for return value of sprd_clk_regmap_init() | Chunyan Zhang | 2019-06-28 | 1 | -1/+4 | |
| | | | | | * | | | | | clk: sprd: Check error only for devm_regmap_init_mmio() | Chunyan Zhang | 2019-06-26 | 1 | -1/+1 | |
| | | | | | * | | | | | clk: sprd: Switch from of_iomap() to devm_ioremap_resource() | Chunyan Zhang | 2019-06-26 | 1 | -1/+6 | |
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| | | | | * | | | | | clk: consoldiate the __clk_get_hw() declarations | Stephen Rothwell | 2019-07-12 | 8 | -4/+13 | |
| | | | | * | | | | | clk: Unexport __clk_of_table | Stephen Boyd | 2019-05-24 | 2 | -4/+1 | |
| | | | | * | | | | | clk: Remove ifdef for COMMON_CLK in clk-provider.h | Stephen Boyd | 2019-05-24 | 1 | -3/+0 | |
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| | | | * | | | | | clk: tegra: Do not enable PLL_RE_VCO on Tegra210 | Thierry Reding | 2019-06-26 | 1 | -1/+0 | |
| | | | * | | | | | clk: tegra: Warn if an enabled PLL is in IDDQ | Thierry Reding | 2019-06-26 | 1 | -1/+5 | |
| | | | * | | | | | clk: tegra: Do not warn unnecessarily | Thierry Reding | 2019-06-26 | 1 | -2/+3 | |
| | | | * | | | | | clk: tegra210: fix PLLU and PLLU_OUT1 | JC Kuo | 2019-06-26 | 1 | -4/+4 | |
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