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* Merge tag 'arm64-perf' of ↵Linus Torvalds2016-03-219-228/+667
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm[64] perf updates from Will Deacon: "I have another mixed bag of ARM-related perf patches here. It's about 25% CPU and 75% interconnect, but with drivers/bus/ languishing without an obvious maintainer or tree, Olof and I agreed to keep all of these PMU patches together. I suspect a whole load of code from drivers/bus/arm-* can be moved under drivers/perf/, so that's on the radar for the future. Summary: - Initial support for ARMv8.1 CPU PMUs - Support for the CPU PMU in Cavium ThunderX - CPU PMU support for systems running 32-bit Linux in secure mode - Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect)" * tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (26 commits) drivers/perf: arm_pmu: avoid NULL dereference when not using devicetree arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC arm-cci: remove unused variable arm-cci: don't return value from void function arm-cci: make private functions static arm-cci: CoreLink CCI-550 PMU driver arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU arm-cci: CCI-500: Work around PMU counter writes arm-cci: Provide hook for writing to PMU counters arm-cci: Add helper to enable PMU without synchornising counters arm-cci: Add routines to save/restore all counters arm-cci: Get the status of a counter arm-cci: write_counter: Remove redundant check arm-cci: Delay PMU counter writes to pmu::pmu_enable arm-cci: Refactor CCI PMU enable/disable methods arm-cci: Group writes to counter arm-cci: fix handling cpumask_any_but return value arm-cci: simplify sysfs attr handling drivers/perf: arm_pmu: implement CPU_PM notifier arm64: dts: Add Cavium ThunderX specific PMU ...
| * drivers/perf: arm_pmu: avoid NULL dereference when not using devicetreeWill Deacon2016-03-211-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c6b90653f1f7 ("drivers/perf: arm_pmu: make info messages more verbose") breaks booting on systems where the PMU is probed without devicetree (e.g by inspecting the MIDR of the current CPU). In this case, pdev->dev.of_node is NULL and we shouldn't try to access its ->fullname field when printing probe error messages. This patch fixes the probing code to use of_node_full_name, which safely handles NULL nodes and removes the "Error %i" part of the string, since it's not terribly useful. Reported-by: Guenter Roeck <private@roeck-us.net> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LCWill Deacon2016-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit 7175f0591eb9 ("arm64: perf: Enable PMCR long cycle counter bit") added initial support for a 64-bit cycle counter enabled using PMCR.LC. Unfortunately, that patch doesn't extend ARMV8_EVTYPE_MASK, so any attempts to set the enable bit are ignored by armv8pmu_pmcr_write. This patch extends the mask to include the new bit. Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: remove unused variableWill Deacon2016-03-011-3/+0
| | | | | | | | | | | | hw_counter is unused in the PMU IRQ handler, so remove it. Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: don't return value from void functionWill Deacon2016-03-011-2/+2
| | | | | | | | | | | | | | pmu_write_register has a void return type, so remove the useless return statement. Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: make private functions staticWill Deacon2016-03-011-2/+2
| | | | | | | | | | | | | | | | cci_pmu_sync_counters and pmu_event_set_period are internal functions to the CCI PMU driver, so make them static to avoid polluting the kernel namespace. Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: CoreLink CCI-550 PMU driverSuzuki K Poulose2016-03-013-5/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ARM CoreLink CCI-550 cache coherent interconnect PMU driver support. The CCI-550 PMU shares all the attributes of CCI-500 PMU, except for an additional master interface (MI-6 - 0xe). CCI-550 requires the same work around as for CCI-500 to write to the PMU counter. Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMUSuzuki K Poulose2016-03-012-109/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CCI-550 PMU shares most of the CCI-500 PMU attributes including the event format, PMU event codes. The only difference is an additional master interface (MI6 - 0xe). Hence we share the driver code for both, except for a model specific event validate method. This patch renames the common CCI500 symbols to CCI5xx, including the Kconfig symbol. No functional changes to the PMU driver. Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: CCI-500: Work around PMU counter writesSuzuki K Poulose2016-03-011-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CCI PMU driver sets the event counter to the half of the maximum value(2^31) it can count before we start the counters via pmu_event_set_period(). This is done to give us the best chance to handle the overflow interrupt, taking care of extreme interrupt latencies. However, CCI-500 comes with advanced power saving schemes, which disables the clock to the event counters unless the counters are enabled to count (PMCR.CEN). This prevents the driver from writing the period to the counters before starting them. Also, there is no way we can reset the individual event counter to 0 (PMCR.RST resets all the counters, losing their current readings). However the value of the counter is preserved and could be read back, when the counters are not enabled. So we cannot reliably use the counters and compute the number of events generated during the sampling period since we don't have the value of the counter at start. This patch works around this issue by changing writes to the counter with the following steps. 1) Disable all the counters (remembering any counters which were enabled) 2) Enable the PMU, now that all the counters are disabled. For each counter to be programmed, repeat steps 3-7 3) Save the current event and program the target counter to count an invalid event, which by spec is guaranteed to not-generate any events. 4) Enable the target counter. 5) Write to the target counter. 6) Disable the target counter 7) Restore the event back on the target counter. 8) Disable the PMU 9) Restore the status of the all the counters Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: Provide hook for writing to PMU countersSuzuki K Poulose2016-03-011-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a hook for writing to CCI PMU counters. This callback can be used for CCI models which requires some extra work to program the PMU counter values. To accommodate group writes and single counter writes, the call back accepts a bitmask of the counter indices which need to be programmed with the given value. Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: Add helper to enable PMU without synchornising countersSuzuki K Poulose2016-03-011-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | On CCI-500 writing to a counter requires turning the PMU on. So, synchronising the counter state should not be performed for such special cases, while turning the PMU on. This patch adds a helper, __cci_pmu_enable_nosync(), without flushing the counter states. Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: Add routines to save/restore all countersSuzuki K Poulose2016-03-011-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Adds helper routines to disable the counter controls for all the counters on the CCI PMU and restore it back, by preserving the original state in caller provided mask. Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: Get the status of a counterSuzuki K Poulose2016-03-011-0/+6
| | | | | | | | | | | | | | | | | | | | Add helper routines to check if the counter is enabled or not. Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: write_counter: Remove redundant checkSuzuki K Poulose2016-03-011-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | pmu_write_counter() is now only called from pmu_write_counters(), which does so for each set index in the given mask, bounded by cci_pmu->num_cntrs. So, there is no need for an extra check to make sure the given counter is valid inside pmu_write_counter. This patch gets rid of that. Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: Delay PMU counter writes to pmu::pmu_enableSuzuki K Poulose2016-03-011-5/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CCI PMU driver always reprograms the counters to a safe value (half of the counter max, = 2^31) before starting the profiling to account for extreme interrupt latencies. Also, the cost of writing to a PMU counter could be very costly on some PMUs(e.g, CCI-500). In order to ammortise the cost of programming the counters, this patch delays the counter writes to pmu::pmu_enable(). We use the PER_HES_ARCH flag to keep track of the counters which need to be programmed. Before turning on the PMU, we go through the counters that were marked for write, and perform the operation in a batch. To unify all the counter writes to pmu_enable(), this patch also makes sure that we disable-and-enable the PMU in the irq handler to program any counters that overflowed. Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: Refactor CCI PMU enable/disable methodsSuzuki K Poulose2016-03-011-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors the CCI PMU driver code a little bit to make it easier share the code for enabling/disabling the CCI PMU. This will be used by the hooks to work around the special cases where writing to a counter is not always that easy(e.g, CCI-500) No functional changes. Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: Group writes to counterSuzuki K Poulose2016-03-011-0/+15
| | | | | | | | | | | | | | | | | | | | | | Add a helper to group the writes to PMU counter, this will be used to delay setting the event period to pmu::pmu_enable() Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: fix handling cpumask_any_but return valueAndrzej Hajda2016-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpumask_any_but returns value >= nr_cpu_ids if there are no more CPUs. The problem has been detected using proposed semantic patch scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2038576 Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm-cci: simplify sysfs attr handlingMark Rutland2016-03-011-75/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need to dynamically initialise attribute pointers when we can get the compiler to do it for us. We also don't need a dev_ext_attribute for the cpumask, as the drvdata for a PMU device is a pointer to struct pmu. Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * drivers/perf: arm_pmu: implement CPU_PM notifierLorenzo Pieralisi2016-02-262-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a CPU is suspended (either through suspend-to-RAM or CPUidle), its PMU registers content can be lost, which means that counters registers values that were initialized on power down entry have to be reprogrammed on power-up to make sure the counters set-up is preserved (ie on power-up registers take the reset values on Cold or Warm reset, which can be architecturally UNKNOWN). To guarantee seamless profiling conditions across a core power down this patch adds a CPU PM notifier to ARM pmus, that upon CPU PM entry/exit from low-power states saves/restores the pmu registers set-up (by using the ARM perf API), so that the power-down/up cycle does not affect the perf behaviour (apart from a black-out period between power-up/down CPU PM notifications that is unavoidable). Cc: Will Deacon <will.deacon@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm64: dts: Add Cavium ThunderX specific PMUJan Glauber2016-02-182-0/+6
| | | | | | | | | | | | | | Add a compatible string for the Cavium ThunderX PMU. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm64: perf: Extend event mask for ARMv8.1Jan Glauber2016-02-181-2/+2
| | | | | | | | | | | | | | | | ARMv8.1 increases the PMU event number space to 16 bit so increase the EVTYPE mask. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm64: perf: Enable PMCR long cycle counter bitJan Glauber2016-02-181-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated. To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before. Original patch from Andrew Pinksi <Andrew.Pinksi@caviumnetworks.com> Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm64/perf: Add Cavium ThunderX PMU supportJan Glauber2016-02-181-1/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support PMU events on Caviums ThunderX SOC. ThunderX supports some additional counters compared to the default ARMv8 PMUv3: - branch instructions counter - stall frontend & backend counters - L1 dcache load & store counters - L1 icache counters - iTLB & dTLB counters - L1 dcache & icache prefetch counters Signed-off-by: Jan Glauber <jglauber@cavium.com> [will: capitalisation] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * arm64: perf: Rename Cortex A57 eventsJan Glauber2016-02-181-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | The implemented Cortex A57 events are strictly-speaking not A57 specific. They are ARM recommended implementation defined events and can be found on other ARMv8 SOCs like Cavium ThunderX too. Therefore rename these events to allow using them in other implementations too. Signed-off-by: Jan Glauber <jglauber@cavium.com> [will: capitalisation and ordering] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * drivers/perf: arm_pmu: make info messages more verboseDirk Behme2016-02-091-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a big.LITTLE system e.g. with Cortex A57 and A53 in case not all cores are online at PMU probe time we might get hw perfevents: failed to probe PMU! hw perfevents: failed to register PMU devices! making it unclear which cores failed, here. Add the device tree full name which failed and the error value resulting in a more verbose and helpful message like hw perfevents: /soc/pmu_a53: failed to probe PMU! Error -6 hw perfevents: /soc/pmu_a53: failed to register PMU devices! Error -6 Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * ARM: perf: Set ARMv7 SDER SUNIDEN bitMartin Fuzzey2016-01-254-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv7 counters other than the CPU cycle counter only work if the Secure Debug Enable Register (SDER) SUNIDEN bit is set. Since access to the SDER is only possible in secure state, it will only be done if the device tree property "secure-reg-access" is set. Without this: Performance counter stats for 'sleep 1': 14606094 cycles # 0.000 GHz 0 instructions # 0.00 insns per cycle After applying: Performance counter stats for 'sleep 1': 5843809 cycles 2566484 instructions # 0.44 insns per cycle 1.020144000 seconds time elapsed Some platforms (eg i.MX53) may also need additional platform specific setup. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com> Signed-off-by: George G. Davis <george_davis@mentor.com> [will: add warning if property is found on arm64] Signed-off-by: Will Deacon <will.deacon@arm.com>
* | Merge tag 'arc-4.6-rc1' of ↵Linus Torvalds2016-03-2138-155/+201
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC architecture updates from Vineet Gupta: - Big Endian io accessors fix [Lada] - Spellos fixes [Adam] - Fix for DW GMAC breakage [Alexey] - Making DMA API 64-bit ready - Shutting up -Wmaybe-uninitialized noise for ARC - Other minor fixes here and there, comments update * tag 'arc-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (21 commits) ARCv2: ioremap: Support dynamic peripheral address space ARC: dma: reintroduce platform specific dma<->phys ARC: dma: ioremap: use phys_addr_t consistenctly in code paths ARC: dma: pass_phys() not sg_virt() to cache ops ARC: dma: non-coherent pages need V-P mapping if in HIGHMEM ARC: dma: Use struct page based page allocator helpers ARC: build: Turn off -Wmaybe-uninitialized for ARC gcc 4.8 ARC: [plat-axs10x] add Ethernet PHY description in .dts arc: use of_platform_default_populate() to populate default bus ARC: thp: unbork !CONFIG_TRANSPARENT_HUGEPAGE build arc: [plat-nsimosci*] use ezchip network driver ARCv2: LLSC: software backoff is NOT needed starting HS2.1c ARC: mm: Use virt_to_pfn() for addr >> PAGE_SHIFT pattern ARC: [plat-nsim] document ranges ARC: build: Better way to detect ISA compatible toolchain ARCv2: Allow enabling PAE40 w/o HIGHMEM ARC: [BE] readl()/writel() to work in Big Endian CPU configuration ARC: [*defconfig] No need to specify CONFIG_CROSS_COMPILE ARC: [BE] Select correct CROSS_COMPILE prefix ARC: bitops: Remove non relevant comments ...
| * | ARCv2: ioremap: Support dynamic peripheral address spaceVineet Gupta2016-03-194-14/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The peripheral address space is architectural address window which is uncached and typically used to wire up peripherals. For ARC700 cores (ARCompact ISA based) this was fixed to 1GB region 0xC000_0000 - 0xFFFF_FFFF. For ARCv2 based HS38 cores the start address is flexible and can be 0xC, 0xD, 0xE, 0xF 000_000 by programming AUX_NON_VOLATILE_LIMIT reg (typically done in bootloader) Further in cas of PAE, the physical address can extend beyond 4GB so need to confine this check, otherwise all pages beyond 4GB will be treated as uncached Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: dma: reintroduce platform specific dma<->physVineet Gupta2016-03-193-5/+14
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: dma: ioremap: use phys_addr_t consistenctly in code pathsVineet Gupta2016-03-195-35/+37
| | | | | | | | | | | | | | | | | | To support dma in physical memory beyond 4GB with PAE40 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: dma: pass_phys() not sg_virt() to cache opsVineet Gupta2016-03-191-2/+2
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: dma: non-coherent pages need V-P mapping if in HIGHMEMVineet Gupta2016-03-191-15/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously a non-coherent page (hardware IOC or simply driver needs) could be handled by cpu with paddr alone (kvaddr used to be needed for coherent mappings to enforce uncached semantics via a MMU mapping). Now however such a page might still require a V-P mapping if it was in physical address space > 32bits due to PAE40, which the CPU can't access directly with a paddr So decouple decision of kvaddr allocation from type of alloc request (coh/non-coh) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: dma: Use struct page based page allocator helpersVineet Gupta2016-03-191-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | vs. the ones which reutne void *, so that we can handle pages > 4GB in subsequent patches Also plug a potential page leak in case ioremap fails Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: build: Turn off -Wmaybe-uninitialized for ARC gcc 4.8Vineet Gupta2016-03-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | linux-next has been reporting gazillion warnings for ARC build and I finally decided to take a bite: http://kisskb.ellerman.id.au/kisskb/buildresult/12638735/ Most of the them are due to -Wmaybe-uninitialized | ../kernel/sysctl.c: In function '__do_proc_doulongvec_minmax': | ../kernel/sysctl.c:1928:12: warning: 'p' may be used uninitialized in this function [-Wmaybe-uninitialized] | ret = tmp - *buf; | ^ | ../kernel/sysctl.c:2342:29: note: 'p' was declared here | char *kbuf = NULL, *p; | ^ | ... | ... Cursory look at code seemed fine and a definite gcc false positive in say kernel/sysctl.c Mystery was why only for ARC (and not with ARM linaro toolchain based off same gcc 4.8). Turns out that -O3 (default for ARC) triggers these and if I enable -O3 for ARM kernel build, I see the same splat. I initially wanted to disable this only for gcc 4.8, but Arnd reported it is seen even on gcc 6.0 for ARM with -O3. Thus better to disable this independent of gcc version. Cc: Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Michal Marek <mmarek@suse.cz> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-kbuild@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [plat-axs10x] add Ethernet PHY description in .dtsAlexey Brodkin2016-03-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e34d65696d2e ("stmmac: create of compatible mdio bus for stmmac driver") broke DW GMAC functionality on ARC AXS10x boards: That's what happens on eth0 up: --------------------------->8------------------------ | libphy: PHY stmmac-0:ffffffff not found | eth0: Could not attach to PHY | stmmac_open: Cannot attach to PHY (error: -19) --------------------------->8------------------------ Simplest solution is to add PHY description in board's .dts. And so we do here. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Rob Herring <robh@kernel.org> Cc: Phil Reid <preid@electromag.com.au> Cc: David S. Miller <davem@davemloft.net> Cc: linux-kernel@vger.kernel.org Cc: netdev@vger.kernel.org Cc: stable@vger.kernel.org # 4.5 Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | arc: use of_platform_default_populate() to populate default busKefeng Wang2016-03-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use helper of_platform_default_populate() in linux/of_platform when possible, instead of calling of_platform_populate() with the default match table. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: thp: unbork !CONFIG_TRANSPARENT_HUGEPAGE buildVineet Gupta2016-03-171-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | linux-next for 4.6-rc1 timeline reported ARC build failures !THP | arch/arc/include/asm/tlbflush.h:29:0: warning: "flush_pmd_tlb_range" redefined [enabled by default] | arch/arc/include/asm/tlbflush.h:29:0: warning: "flush_pmd_tlb_range" redefined [enabled by default] | arch/arc/include/asm/tlbflush.h:29:0: warning: "flush_pmd_tlb_range" redefined [enabled by default] Turns out that commit ("mm/thp/migration: switch from flush_tlb_range to flush_pmd_tlb_range") triggered the issue while the problem was in ARC code where THP specific helpers were not guarded with #ifdef. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | arc: [plat-nsimosci*] use ezchip network driverLada Trimasova2016-03-156-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since ezchip network driver was adapted to little endian architecture this patch provides the corresponding arch/arc/{boot/dts,configs}/ updates so we can switch over to this device-model/driver for OSCI platform. Cc: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Lada Trimasova <ltrimas@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARCv2: LLSC: software backoff is NOT needed starting HS2.1cVineet Gupta2016-03-152-6/+1
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: mm: Use virt_to_pfn() for addr >> PAGE_SHIFT patternVineet Gupta2016-03-122-17/+11
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [plat-nsim] document rangesVineet Gupta2016-03-121-1/+2
| | | | | | | | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: build: Better way to detect ISA compatible toolchainVineet Gupta2016-03-122-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARC architecture has 2 instruction sets: ARCompact/ARCv2. While same gcc supports compiling for either (using appropriate toggles), we can't use the same toolchain to build kernel because libgcc needs to be unique and the toolchian (uClibc based) is not multilibed. uClibc toolchain is convenient since it allows all userspace and kernel to be built with a single install for an ISA. This however means 2 gnu installs (with same triplet prefix) are needed for building for 2 ISA and need to be in PATH. As developers we keep switching the builds, but would occassionally fail to update the PATH leading to usage of wrong tools. And this would only show up at the end of kernel build when linking incompatible libgcc. So the initial solution was to have gcc define a special preprocessor macro DEFAULT_CPU_xxx which is unique for default toolchain configuration. Claudiu proposed using grep for an existing preprocessor macro which is again uniquely defined per ISA. Cc: Michal Marek <mmarek@suse.cz> Suggested-by: Claudiu Zissulescu <claziss@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARCv2: Allow enabling PAE40 w/o HIGHMEMVineet Gupta2016-03-121-1/+0
| | | | | | | | | | | | | | | | | | | | | This allows for regression testing in PAE specific code as we lack a 32+ bit physical memory platform other than nSIM. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [BE] readl()/writel() to work in Big Endian CPU configurationLada Trimasova2016-03-121-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | read{l,w}() write{l,w}() primitives should use le{16,32}_to_cpu() and cpu_to_le{16,32}() respectively to ensure device registers are read correctly in Big Endian CPU configuration. Per Arnd Bergmann | Most drivers using readl() or readl_relaxed() expect those to perform byte | swaps on big-endian architectures, as the registers tend to be fixed endian This was needed for getting UART to work correctly on a Big Endian ARC. The ARC accessors originally were fine, and the bug got introduced inadventently by commit b8a033023994 ("ARCv2: barriers") Fixes: b8a033023994 ("ARCv2: barriers") Link: http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: stable@vger.kernel.org [4.2+] Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lada Trimasova <ltrimas@synopsys.com> [vgupta: beefed up changelog, added Fixes/stable tags] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [*defconfig] No need to specify CONFIG_CROSS_COMPILEVineet Gupta2016-03-1112-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem is with CONFIG_CPU_BIG_ENDIAN=y we still needed .config fixup to override the the defconfig prefix to arceb-linux- So remove these from defconfig and let user pass this via CROSS_COMPILE environment var or use the default for ENDIAN (per previous patch) No other arch carries them in defconfigs anyways ! Cc: Noam Camus <noamc@ezchip.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Anton Kolesov <akolesov@synosys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: [BE] Select correct CROSS_COMPILE prefixVineet Gupta2016-03-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows CONFIG_CPU_BIG_ENDIAN=y to build correctly out of the box, w/o any other tweaks. Cc: Noam Camus <noamc@ezchip.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Anton Kolesov <akolesov@synosys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: bitops: Remove non relevant commentsVineet Gupta2016-03-111-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | commit 80f420842ff42 removed the ARC bitops microoptimization but failed to prune the comments to same effect Fixes: 80f420842ff42 ("ARC: Make ARC bitops "safer" (add anti-optimization)") Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| * | ARC: Fix misspellings in comments.Adam Buchbinder2016-03-118-12/+12
| | | | | | | | | | | | | | | Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* | | Merge branch 'for_linus' of ↵Linus Torvalds2016-03-2116-437/+471
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs Pull UDF and quota updates from Jan Kara: "This contains a rewrite of UDF handling of filename encoding to fix remaining overflow issues from Andrew Gabbasov and quota changes to support new Q_[X]GETNEXTQUOTA quotactl for VFS quota formats" * 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs: quota: Fix possible GPF due to uninitialised pointers ext4: Make Q_GETNEXTQUOTA work for quota in hidden inodes quota: Forbid Q_GETQUOTA and Q_GETNEXTQUOTA for frozen filesystem quota: Fix possible races during quota loading ocfs2: Implement get_next_id() quota_v2: Implement get_next_id() for V2 quota format quota: Add support for ->get_nextdqblk() for VFS quota udf: Merge linux specific translation into CS0 conversion function udf: Remove struct ustr as non-needed intermediate storage udf: Use separate buffer for copying split names udf: Adjust UDF_NAME_LEN to better reflect actual restrictions udf: Join functions for UTF8 and NLS conversions udf: Parameterize output length in udf_put_filename quota: Allow Q_GETQUOTA for frozen filesystem quota: Fixup comments about return value of Q_[X]GETNEXTQUOTA
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