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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
Merge "soc/tegra: Changes for v4.7-rc1" from Thierry Reding:
This contains a bunch of preparatory patches to the PMC driver which are
a prerequisite to moving the driver to generic power domains.
* tag 'tegra-for-4.7-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: Update NVIDIA PMC for Tegra
soc/tegra: pmc: Wait for powergate state to change
soc/tegra: pmc: Ensure GPU partition can be toggled on/off by PMC
soc/tegra: pmc: Remove additional check for a valid partition
soc/tegra: pmc: Fix verification of valid partitions
soc/tegra: pmc: Fix testing of powergate state
soc/tegra: pmc: Change powergate and rail IDs to be an unsigned type
soc/tegra: pmc: Protect public functions from potential race conditions
soc/tegra: pmc: Restore base address on probe failure
soc/tegra: pmc: Remove non-existing L2 partition for Tegra124
soc/tegra: pmc: Remove non-existing power partitions for Tegra210
soc/tegra: pmc: Remove debugfs entry on probe failure
soc/tegra: pmc: Fix sparse warning for tegra_pmc_init_tsense_reset()
soc/tegra: pmc: Add missing structure members to kernel-doc
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Add the PMC driver compatible strings for Tegra132 and Tegra210.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Currently, the function tegra_powergate_set() simply sets the desired
powergate state but does not wait for the state to change. In most cases
we should wait for the state to change before proceeding. Currently,
there is a case for Tegra114 and Tegra124 devices where we do not wait
when starting the secondary CPU as this is not necessary. However, this
is only done at boot time and so waiting here will only have a small
impact on boot time. Therefore, update tegra_powergate_set() to wait
when setting the powergate.
By adding this feature, we can also eliminate the polling loop from
tegra30_boot_secondary().
A function has been added for checking the status of the powergate and
so update the tegra_powergate_is_powered() to use this macro as well.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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For Tegra124 and Tegra210, the GPU partition cannot be toggled on and
off via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the
partition is simply powered up and down via an external regulator.
For these devices, there is a separate register for controlling the
signal clamping of the partition and this is described in the PMC SoC
data by the "has_gpu_clamp" variable. Use this variable to determine if
the GPU partition can be controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0
register and ensure that no one can incorrectly try to toggle the GPU
partition via the APBDEV_PMC_PWRGATE_TOGGLE_0 register.
Furthermore, we cannot use the APBDEV_PMC_PWRGATE_STATUS_0 register to
determine if the GPU partition is powered for Tegra124 and Tegra210.
However, if the GPU partition is powered, then the signal clamp for the
GPU partition should be removed and so use bit 0 of the
APBDEV_PMC_GPU_RG_CNTRL_0 register to determine if the clamp has been
removed (bit[0] = 0) and the GPU partition is powered.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The function tegra_powergate_is_powered() verifies that the partition
being queried is valid and so there is no need to check this before
calling tegra_powergate_is_powered() in powergate_show(). So remove this
extra check.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra power partitions are referenced by numerical IDs which are the
same values programmed into the PMC registers for controlling the
partition. For a given device, the valid partition IDs may not be
contiguous and so simply checking that an ID is not greater than the
maximum ID supported may not mean it is valid. Fix this by checking if
the powergate is defined in the list of powergates for the Tegra SoC.
Add a helper function for checking valid powergates and use where we
need to verify if the powergate ID is valid or not.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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In tegra_powergate_set() the state of the powergates is read and OR'ed
with the bit for the powergate of interest. This unsigned 32-bit value
is then compared with a boolean value to test if the powergate is
already in the desired state. When turning on a powergate, apart from
the powergate that is represented by bit 0, this test will always
return false and so we may attempt to turn on the powergate when it is
already on.
After OR'ing the bit for the powergate, check if the result is not equal
to zero before comparing with the boolean value. Add a helper function
to return the current state of a powergate and use this in both
tegra_powergate_set() and tegra_powergate_is_powered() where we check
the powergate status.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra powergate and rail IDs are always positive values and so change
the type to be unsigned and remove the tests to see if the ID is less
than zero. Update the Tegra DC powergate type to be an unsigned as well.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The PMC base address pointer is initialised during early boot so that
early platform code may used the PMC public functions. During the probe
of the PMC driver the base address pointer is mapped again and the initial
mapping is freed. This exposes a window where a device accessing the PMC
registers via one of the public functions, could race with the updating
of the pointer and lead to a invalid access. Furthermore, the only
protection between multiple devices attempting to access the PMC registers
is when setting the powergate state to on or off. None of the other public
functions that access the PMC registers are protected.
Use the existing mutex to protect paths that may race with regard to
accessing the PMC registers.
Note that functions tegra_io_rail_prepare()/poll() either return a
negative value on failure or zero on success. Therefore, it is not
necessary to check if the return value is less than zero and so only
test that the return value is not zero to test for failure. This
simplifies the error handling with the mutex locking in place.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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During early initialisation, the PMC registers are mapped and the PMC SoC
data is populated in the PMC data structure. This allows other drivers
access the PMC register space, via the public Tegra PMC APIs, prior to
probing the PMC device.
When the PMC device is probed, the PMC registers are mapped again and if
successful the initial mapping is freed. If the probing of the PMC device
fails after the registers are remapped, then the registers will be
unmapped and hence the pointer to the PMC registers will be invalid. This
could lead to a potential crash, because once the PMC SoC data pointer is
populated, the driver assumes that the PMC register mapping is also valid
and a user calling any of the public Tegra PMC APIs could trigger an
exception because these APIs don't check that the mapping is still valid.
Fix this by updating the mapping and freeing the original mapping only if
probing the PMC device is successful.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra124 does not have an L2 power partition and the L2 cache is part of
the cluster 0 non-CPU (CONC) partition. Remove the L2 as a valid
partition for Tegra124. The TRM also shows that there is no L2 partition
for Tegra124.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The power partitions L2, HEG, CELP and C1NC do not exist on Tegra210 but
were incorrectly documented in the TRM. These will be removed from the
TRM and so also remove their definitions.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The debugfs entry for the PMC device will not be removed if the probe of
the device fails to register the restart handler. This leaves behind the
dangling debugfs entry with no driver backing it. Remove the entry to
avoid this.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Sparse reports the following warning for tegra_pmc_init_tsense_reset():
drivers/soc/tegra/pmc.c:741:6: warning: symbol 'tegra_pmc_init_tsense_reset' was not declared. Should it be static?
This function is only used internally by the PMC driver and so fix this
by making it static.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Some members of the tegra_pmc structure are missing from the kernel-doc
comment for this structure. Add the missing members.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers
Merge "move Versatile flash protection to the device tree" from Linus Walleij:
This is a set of patches removing the board file code
for Versatile flash handling and instead moving it over
to the device tree and a special add-on file.
* tag 'versatile-flash-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: integrator: move flash registration to device tree
ARM: versatile: move flash registration to the device tree
mtd: augment the "arm,versatile-flash" bindings
mtd: physmap_of: add a hook for Versatile write protection
Acked-by: Brian Norris <computersforpeace@gmail.com>
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The flash on the Integrator was already defined by the device
tree, but VPP control and flash protection was in the
boardfiles. Simply add the compatible string
"arm,versatile-flash" and the special add-on code for flash
programming voltage and protection kicks in in the MTD
layer.
Remove the board file code and augment the device tree in
one go for seamless transition.
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the boardfile definition of the flash memory in the
Versatile board into the device tree. The flash was already
defined with the property "arm,versatile-flash" which was
not handled by the kernel: instead define it as compatible
also with "cfi-flash" so it detects properly, and delete the
corresponding boardfile code so we get a smooth transition.
The old compatible string "arm,versatile-flash" is reused to
indicate to the MTD physmap subsystem that this flash requires
special VPP handling. (See separate patch.)
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The bindings for the "arm,versatile-flash" device was merged in
commit 3ba7222ac992d24d09ccd0b55940b54849eef752
"arm/versatile: Add device tree support" but was never used
for anything.
Versatile flash chips are actually just standard CFI chips,
but they have one or two bits in a system controller to control
VPP and write protection. Let's use this compatible string in
conjunction with "cfi-flash" to indicate that we have a
normal CFI flash with some extra Versatile-specific protection.
Cc: devicetree@vger.kernel.org
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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In order to support device tree probing of Versatile NOR flash
chips, there must be a way to add the VPP (write protection)
enable/disable callback. The register in question is in the
system controllers of these machines. Apart from this quirk,
the ARM flash chips are standard CFI flash chips from various
vendors.
Additionally, the Integrator/AP require you to set up the external
bus interface (EBI) to allow writes to the chip select where the
flash memory is connected.
Solve this by looking for the arm,versatile-flash compatible
string in the flash device tree node. In the driver,
add a special hook to check for the various Versatile syscons and
register a callback for .set_vpp() if this compatible is present.
Provide a special Kconfig entry for the addon hook so it will
not be compiled in if the Versatile boards are not supported.
Stubs in the header file make sure the impact will be zero on
other platforms. (Compilers optimze this out.)
With this patch, a large slew of ARM board file code can be
removed.
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers
Rockchip soc-specific driver changes containing support for the
rk3399 powerdomains and necessary infrastructure changes to
accomodate them - like supporting nested powerdomains here.
* tag 'v4.7-rockchip-drivers-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
soc: rockchip: power-domain: check the existing of regmap
soc: rockchip: power-domain: Modify power domain driver for rk3399
dt-bindings: add binding for rk3399 power domains
dt-bindings: add power-domain header for RK3399 SoCs
soc: rockchip: power-domain: add support for sub-power domains
soc: rockchip: power-domain: allow domains only handling idle requests
soc: rockchip: power-domain: make idle handling optional
Signed-off-by: Olof Johansson <olof@lixom.net>
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Check return value of syscon_node_to_regmap for
rockchip_pm_domain_probe. If err value is returned, probe
procedure should abort.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This driver is modified to support RK3399 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[small indentation fixups]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add binding documentation for the power domains
found on Rockchip RK3399 SoCs
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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According to a description from TRM, add all the power domains
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences,
which needs to have more than one power domain enabled to be operational.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[restructured error handling in subdomain-addition]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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On some Rockchip SoC there exist child-domains only handling their
idle state with the actual power-state handled by a (shared) parent-
domain.
So allow such types of domains. For them, we can determine their
state (on/off) by checking the inverse idle-state instead.
There exist one special case if both idle as well power handling
were set as not present, but as the domain-data is defined in the
code itself, we can expect the reasonable developer to define them
in a correct way, without adding more checks.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Not all new socs need to handle idle states on domain state changes,
so add the possibility to make them optional.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Renesas ARM Based SoC Simple PM Bus Updates for v4.7
* Use ARCH_RENESAS in Kconfig
* tag 'renesas-simple-pm-bus-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
bus: simple-pm-bus: Use ARCH_RENESAS
Signed-off-by: Olof Johansson <olof@lixom.net>
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Make use of ARCH_RENESAS in place of ARCH_SHMOBILE.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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next/drivers
Reset controller changes for v4.7
- add support for shared reset controls
- remove global variables from the lpc18xx driver
* tag 'reset-for-4.7' of git://git.pengutronix.de/git/pza/linux:
reset: lpc18xx: get rid of global variables for restart notifier
reset: Add support for shared reset controls
reset: Share struct reset_control between reset_control_get calls
reset: Make [of_]reset_control_get[_foo] functions wrappers
Signed-off-by: Olof Johansson <olof@lixom.net>
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Moving the notifier_block into the drivers priv struct allows us
to retrive the priv struct with container_of and remove the
global variables.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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In some SoCs some hw-blocks share a reset control. Add support for this
setup by adding new:
reset_control_get_shared()
devm_reset_control_get_shared()
devm_reset_control_get_shared_by_index()
methods to get a reset_control. Note that this patch omits adding of_
variants, if these are needed later they can be easily added.
This patch also changes the behavior of the existing exclusive
reset_control_get() variants, if these are now called more then once
for the same reset_control they will return -EBUSY. To catch existing
drivers triggering this error (there should not be any) a WARN_ON(1)
is added in this path.
When a reset_control is shared, the behavior of reset_control_assert /
deassert is changed, for shared reset_controls these will work like the
clock-enable/disable and regulator-on/off functions. They will keep a
deassert_count, and only (re-)assert the reset after reset_control_assert
has been called as many times as reset_control_deassert was called.
Calling reset_control_assert without first calling reset_control_deassert
is not allowed on a shared reset control. Calling reset_control_reset is
also not allowed on a shared reset control.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Now that struct reset_control no longer stores the device pointer for
the device calling reset_control_get we can share a single struct
reset_control when multiple calls to reset_control_get are made for
the same reset line (same id / index).
This is a preparation patch for adding support for shared reset lines.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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With both the regular, _by_index and _optional variants we already have
quite a few variants of [of_]reset_control_get[_foo], the upcoming
addition of shared reset lines support makes this worse.
This commit changes all the variants into wrappers around common core
functions. For completeness sake this commit also adds a new
devm_get_reset_control_by_index wrapper.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers
Qualcomm ARM Based SoC Updates for v4.7
* Add stubs for smem_state to fix build issues
* Fix module usage in SPM driver
* Add i2c and spi entries into QCOM MAINTAINERS entry
* Add SMD multi channel support
* Add clks to QCOM MAINTAINERS
* tag 'qcom-soc-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
soc: qcom: smd: Support opening additional channels
soc: qcom: smd: Support multiple channels per sdev
soc: qcom: smd: Refactor channel open and close handling
soc: qcom: smd: Split discovery and state change work
soc: qcom: smd: Introduce callback setter
drivers: qcom: spm: avoid module usage in non-modular SPM driver
soc: qcom: smem_state: Add stubs for disabled smem_state
MAINTAINERS: add qcom clocks to the maintainers list
MAINTAINERS: add qcom i2c and spi drivers to list
Signed-off-by: Olof Johansson <olof@lixom.net>
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With the qcom_smd_open_channel() API we allow SMD devices to open
additional SMD channels, to allow implementation of multi-channel SMD
devices - like Bluetooth.
Channels are opened from the same edge as the calling SMD device is tied
to.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch allows chaining additional channels to a SMD device, enabling
implementation of multi-channel SMD devies - like Bluetooth.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Refactor opening and closing of channels into two separate functions
instead of open coding this in the various places.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Split the two steps of channel discovery and state change handling into
two different workers. This allows for new channels to be found while
we're are probing, which is required as we introduce multi-channel
support.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Introduce a setter for the callback function pointer to clarify the
locking around the operation and to reduce some duplication.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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SPM driver provides cpuidle support on some QC SoC's. The functionality
is non-modular and there is no need for module support. Convert module
platform init to builtin platform driver init. The driver functionality
is not affected by this change.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch adds qcom clock drivers to the QCOM/MSM support list so that
get_maintainer.pl can pick up correct cc list.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch adds i2c-qup and spi-qup drivers in to the qualcomm
maintainer list, so that get maintainers scripts can get correct people
to send patch to.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Ivan T. Ivanov <iivanov.xz.@gmail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Pull ARM fixes from Russell King:
"A couple of small fixes, and wiring up the new syscalls which appeared
during the merge window"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8550/1: protect idiv patching against undefined gcc behavior
ARM: wire up preadv2 and pwritev2 syscalls
ARM: SMP enable of cache maintanence broadcast
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It was reported that a kernel with CONFIG_ARM_PATCH_IDIV=y stopped
booting when compiled with the upcoming gcc 6. Turns out that turning
a function address into a writable array is undefined and gcc 6 decided
it was OK to omit the store to the first word of the function while
still preserving the store to the second word.
Even though gcc 6 is now fixed to behave more coherently, it is a
mystery that gcc 4 and gcc 5 actually produce wanted code in the kernel.
And in fact the reduced test case to illustrate the issue does indeed
break with gcc < 6 as well.
In any case, let's guard the kernel against undefined compiler behavior
by hiding the nature of the array location as suggested by gcc
developers.
Reference: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70128
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reported-by: Marcin Juszkiewicz <mjuszkiewicz@redhat.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: stable@vger.kernel.org # v4.5
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Wire up the preadv2 and pwritev2 syscalls for ARM.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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