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* pinctrl: armada-37xx: Add pin controller support for Armada 37xxGregory CLEMENT2017-04-244-2/+658
| | | | | | | | | | | | The Armada 37xx SoC come with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. This constraint is reflected in the design of the driver: only the group related functions are implemented. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllersGregory CLEMENT2017-04-242-3/+187
| | | | | | | | | | | | | Document the device tree binding for the pin controllers found on the Armada 37xx SoCs. Update the binding documention of the xtal clk which is a subnode of this syscon node. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> [Fixed gpios node] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: core: Make pinctrl_init_controller() staticAndy Shevchenko2017-04-241-3/+3
| | | | | | | | | | | | pinctrl_init_controller() is not used outside core.c, thus make it static and prevent compiler to warn. drivers/pinctrl/core.c:1943:21: warning: no previous prototype for ‘pinctrl_init_controller’ [-Wmissing-prototypes] struct pinctrl_dev *pinctrl_init_controller(struct pinctrl_desc *pctldesc, ^~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: generic: Add bi-directional and output-enableJacopo Mondi2017-04-113-0/+8
| | | | | | | | | | | | | | | | Add bi-directional and output-enable pin configuration properties. bi-directional allows to specify when a pin shall operate in input and output mode at the same time. This is particularly useful in platforms where input and output buffers have to be manually enabled. output-enable is just syntactic sugar to specify that a pin shall operate in output mode, ignoring the provided argument. This pairs with input-enable pin configuration option. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: aspeed: Fix unused-const-variable warningsAndrew Jeffery2017-04-111-6/+6
| | | | | | | | Three video input signals suffered from a search/replace failure in some copied code. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'samsung-pinctrl-4.12' of ↵Linus Walleij2017-04-102-25/+83
|\ | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers update for v4.12: 1. Add support for pad retention control through pinctrl drivers which moves us forward to better runtime PM of pinctrl, clocks, power domains and other devices. 2. Fix GPIO hogs by registering pinctrl before registering gpiolib. 3. Use devm-like interface.
| * pinctrl: samsung: Use devres version of gpiochip_add_dataCharles Keepax2017-03-231-7/+2
| | | | | | | | | | | | | | | | Use devm_gpiochip_add_data to simplify the error path in samsung_gpiolib_register. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * pinctrl: samsung: Register pinctrl before GPIOCharles Keepax2017-03-231-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we request a GPIO hog, then gpiochip_add_data will attempt to request some of its own GPIOs. The driver also uses gpiochip_generic_request which means that for any GPIO request to succeed the pinctrl needs to be registered. Currently however the driver registers the GPIO and then the pinctrl meaning all GPIO hog requests will fail, which then in turn causes the whole driver to fail probe. Fix this up by ensuring we register the pinctrl first. This does require us to manually set the GPIO base for the pinctrl. Fortunately the driver already assigns a fixed GPIO base, in samsung_gpiolib_register, and uses the same calculation it does for the pin_base. Meaning the two will always be the same and allowing us to reuse the pinbase and avoid the issue. Although currently there are no users of GPIO hogs in mainline there are plenty of Samsung based boards that are widely used for development purposes of other hardware. Indeed we hit this issue whilst attaching some additional hardware to an Arndale system. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCsMarek Szyprowski2017-03-231-0/+58
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for retention control for Exynos5433 SoCs. Three groups of pins has been defined for retention control: common shared group for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and separate control for FSYS and AUD pin banks, for which PMU retention registers match whole banks. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * pinctrl: samsung: Ensure that pad retention is disabled on driver initMarek Szyprowski2017-03-231-0/+5
| | | | | | | | | | | | | | | | | | | | When pin controller device is a part of power domain, there is no guarantee that the power domain was not turned off and then on during boot process before probing of the pin control driver. If it happened, then pin control driver should ensure that pad retention is turned off during its probe call. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
* | pinctrl: at91-pio4: handle suspend to ramAlexandre Belloni2017-04-071-6/+28
| | | | | | | | | | | | | | | | When suspending to RAM, the power to the core is cut and the register values are lost. Save and restore more registers than just IMR. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Documentation: pinctrl: Add "pinmux" propertyJacopo Mondi2017-04-071-5/+41
| | | | | | | | | | | | | | | | | | Document "pinmux" property as part of generic pin controller documentation. Fix 2 minor typos in documentation while at there. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: pinmux: Fix kerneldoc for pinmux_generic_add_function()Geert Uytterhoeven2017-04-071-1/+1
| | | | | | | | | | | | | | | | | | Correct the incorrect function name and description. Fixes: a76edc89b100e4fe ("pinctrl: core: Add generic pinctrl functions for managing groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Add pincontrol driver for ARTPEC-6 SoCJesper Nilsson2017-04-074-0/+1005
| | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl driver support for the Axis ARTPEC-6 SoC. There are only some pins that actually have different functions available, but all can control bias (pull-up/-down) and drive strength. Code originally written by Chris Paterson. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Add bindings for ARTPEC-6 pinmuxJesper Nilsson2017-04-072-0/+86
| | | | | | | | | | | | | | | | | | Add the bindings for the pinmux functions in the ARTPEC-6 SoC, including bias and drive strength. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8b: rename the NAND DQS pin definitionsMartin Blumenstingl2017-04-071-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND DQS pins are currently named nand_dqs_0 and nand_dqs_1. However, they both seem to have the same function, just exposed on different pins (unlike the ethernet TX pins for example, where there's eth_txd0..3 - all of these can be active at the same time as they are different data lines). Rename the NAND DQS pins to nand_dqs_15 and nand_dqs_18 to reflect that it's the same functionality just exposed on different pins (BOOT_15 and BOOT_18). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: meson8b: fix the NAND DQS pinsMartin Blumenstingl2017-04-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The nand_groups table uses different names for the NAND DQS pins than the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0). This prevents using the NAND DQS pins in the devicetree. Fix this by ensuring that the GROUP() definition and the meson8b_cbus_groups use the same name for these pins. Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'sh-pfc-for-v4.12-tag2' of ↵Linus Walleij2017-04-044-3419/+6437
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.12 (take two) - Add basic support for the Pin Function Controller on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in many ways.
| * | pinctrl: sh-pfc: r8a7795: Add SCIF_CLK supportGeert Uytterhoeven2017-03-301-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and a function for SCIF_CLK on R-Car H3 ES2.0. SCIF_CLK is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF serial ports. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
| * | pinctrl: sh-pfc: r8a7795: Add SCIF supportGeert Uytterhoeven2017-03-301-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups, and functions for all SCIF serial ports on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
| * | pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0Geert Uytterhoeven2017-03-304-3690/+6409
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Pin Function Controller module in the R-Car H3 ES2.0 differs from ES1.x in many ways. The goal is twofold: 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary for now, 2. Make it clear which code supports ES1.x, so it can easily be identified and removed later, when production SoCs are deemed ubiquitous. Hence this patch: 1. Extracts the support for R-Car H3 ES1.x into a separate file, as the differences are quite large, 2. Adds code for detecting the SoC revision at runtime using the new soc_device_match() API, and selecting pinctrl tables for the actual SoC revision, 3. Replaces the core register and bitfield definitions by their counterparts for R-Car H3 ES2.0. The addition of pins, groups, and functions for the various on-chip devices is left to subsequent patches. The R-Car H3 ES2.0 register and bitfield definitions were extracted from a patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
* | | pinctrl: meson: gxl: add spdif output pinsJerome Brunet2017-03-281-0/+18
| | | | | | | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson: gxl: add i2s output pinsJerome Brunet2017-03-281-0/+31
| | | | | | | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson: gxbb: add spdif output pinsJerome Brunet2017-03-281-0/+18
| | | | | | | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson: gxbb: add i2s output pinsJerome Brunet2017-03-281-0/+31
| | | | | | | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson: use gpio-ranges from DTNeil Armstrong2017-03-281-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When trying to add a gpio-hog, we enter a weird loop where the gpio-ranges is needed when gpiochip_add_data() is called but in the current implementation the ranges are added from the driver afterwards. A simple solution is to rely on the DR gpio-ranges attribute and remove the call to gpiochip_add_pin_range(). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | MAINTAINERS: pinctrl: Add git tree to Samsung pinctrl entryKrzysztof Kozlowski2017-03-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Git tree on @kernel.org for maintaining the Samsung pinctrl drivers. The tree will be maintained in a shared model between current Samsung pinctrl maintainers. Pull requests will be going to Linus Walleij. Also add the patchwork for linux-samsung-soc mailing list which will be used for handling the patches. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: meson-gxl: Fix inverted registers and add missing pinsNeil Armstrong2017-03-281-15/+68
| | | | | | | | | | | | | | | | | | | | | | | | Fix some inverted bit numbers in some pinctrl groups and add missing pins and groups to be in pair with the GXBB pinctrl pins definition. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: rockchip: avoid hardirq-unsafe functions in irq_chipJohn Keeping2017-03-281-4/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With real-time preemption, regmap functions cannot be used in the implementation of irq_chip since they use spinlocks which may sleep. Move the setting of the mux for IRQs to an irq_bus_sync_unlock handler where we are allowed to sleep. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: rockchip: split out verification of mux settingsJohn Keeping2017-03-281-16/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to avoid calling regmap functions from irq handlers, so the next commit is going to move the call to rockchip_set_mux() into an irq_bus_sync_unlock handler. But we can't return an error from there so we still need to check the settings from rockchip_irq_set_type() and we will use this new rockchip_verify_mux() function from there. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: rockchip: convert to raw spinlockJohn Keeping2017-03-281-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This lock is used from rockchip_irq_set_type() which is part of the irq_chip implementation and thus must use raw_spinlock_t as documented in Documentation/gpio/driver.txt. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | pinctrl: rockchip: remove unnecessary lockingJohn Keeping2017-03-281-31/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | regmap_update_bits does its own locking and everything else accessed here is a local variable so there is no need to lock around it. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'sh-pfc-for-v4.12-tag1' of ↵Linus Walleij2017-03-242-87/+91
|\| | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.12 - Fixes and cleanups.
| * | pinctrl: sh-pfc: Update info pointer after SoC-specific initGeert Uytterhoeven2017-03-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the sh_pfc_soc_info pointer after calling the SoC-specific initialization function, as it may have been updated to e.g. handle different SoC revisions. This makes sure the correct subdriver name is printed later. Fixes: 0c151062f32c9db8 ("sh-pfc: Add support for SoC-specific initialization") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7795: Restore sort orderGeert Uytterhoeven2017-03-211-85/+86
| | | | | | | | | | | | | | | | | | | | | Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong positions. Restore sort order (alphabetically, per group). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | pinctrl: sh-pfc: r8a7795: Fix hscif2_clk_b and hscif4_ctrlGeert Uytterhoeven2017-03-211-2/+2
| |/ | | | | | | | | | | | | Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[]. Fixes: a56069c46c102710 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | pinctrl: cherryview: Add support for GMMR GPIO opregionHans de Goede2017-03-231-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some Cherry Trail devices the ASL uses the GMMR GPIO to access GPIOs so as to serialize MMIO accesses to GPIO registers with the OS, because: "Due to a silicon issue, a shared lock must be used to prevent concurrent accesses across the 4 GPIO controllers. See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), errata #CHT34, for further information." This commit adds support for this opregion, this fixes a number of ASL errors on my Ezpad mini3 tablet and makes the otg port device/host muxing which is controlled in firmware on this model work properly. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip: rename RK1108 to RV1108Andy Yan2017-03-232-39/+39
| | | | | | | | | | | | | | | | | | Rockchip finally named the SOC as RV1108, so change it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> [adapted rk1108 dtsi to keep bisectability] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: rockchip,pinctrl: rename RK1108 to RV1108Andy Yan2017-03-231-5/+12
| | | | | | | | | | | | | | | | | | | | Rockchip finally named the SOC as RV1108, so change it. Also move the compatible list to one compatible per line. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip: add irq_enable & irq_disable opsJeffy Chen2017-03-231-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we are trying to enable/disable the clk of irq's gpio bank when unmask/mask irq. But the kernel's "lazy disable approach" will skip masking irq when the irq chip doesn't support irq_disable ops. So we may hit this case: irq_enable-> enable clk irq_disable-> noop irq_enable-> enable clk again irq_disable-> noop Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: uniphier: make drivers non-modularMasahiro Yamada2017-03-239-72/+38
| | | | | | | | | | | | | | | | At first these drivers were written as tristate, but the module usecases are actually not tested. Make all of them boolean. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: uniphier: remove obsoleted compatiblesMasahiro Yamada2017-03-238-42/+23
| | | | | | | | | | | | | | | | | | | | Since commit 3e030b0b4e46 ("pinctrl: uniphier: allow to have pinctrl node under syscon node"), this driver has kept compatibility for the old DT files. Several releases have passed since then, so remove the obsoleted compatibles and clean up the code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: gxl: add the missing PWM pin definitionsMartin Blumenstingl2017-03-231-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the missing PWM pins on Meson GXL SoCs, namely: - PWM_A - PWM_B - PWM_C - PWM_F (GPIOX_7 and GPIOCLK_1 can be selected as output) - PWM_AO_A (GPIOAO_3 and GPIOAO_8 can be selected as output) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sunxi: make use of raw_spinlock variantsJulia Cartwright2017-03-162-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi pinctrl driver currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: sirf: atlas7: make use of raw_spinlock variantsJulia Cartwright2017-03-161-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sirf atlas7 pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: amd: make use of raw_spinlock variantsJulia Cartwright2017-03-162-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The amd pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: bcm: make use of raw_spinlock variantsJulia Cartwright2017-03-162-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The bcm pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: qdf2xxx: add names to the gpiosTimur Tabi2017-03-161-2/+12
| | | | | | | | | | | | | | | | | | | | The sysfs and debugfs entries for pin control drivers work better when the individual pins are given real names, even if they are all just "gpio0", "gpio1", etc. Signed-off-by: Timur Tabi <timur@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip: Add input schmitt support for rk3328david.wu2017-03-141-0/+23
| | | | | | | | | | | | Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: rockchip：Add input schmitt supportdavid.wu2017-03-141-0/+73
| | | | | | | | | | | | | | | | | | To prevent external signal crosstalk, some pins need to enable input schmitt, like i2c pins, 32k-input pin and so on. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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