linux - linux

	Commit message (Collapse)	Author	Age	Files	Lines
*	Documentation: bindings: add the Berlin CPU control doc	Antoine Ténart	2014-06-16	1	-0/+16
\| \| \| \| \| \| \| \|	Document the CPU control compatible, needed for the SMP support on Marvell Berlin SoCs. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*	dt-binding: ARM: add pinctrl binding docs for Marvell Berlin2 SoCs	Antoine Tenart	2014-05-19	1	-0/+54
\| \| \| \| \| \| \| \| \|	Add pin control binding documentation to the SoC binding documentaion as pinctrl is part of chip/system control registers. The documentation also explains how to configure this group based controller. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*	dt-binding: ARM: add clock binding docs for Marvell Berlin2 SoCs	Sebastian Hesselbarth	2014-05-19	1	-0/+47
\| \| \| \| \| \| \| \|	This adds mandatory device tree binding documentation for the clock related IP found on Marvell Berlin2 (BG2, BG2CD, and BG2Q) SoCs to the Berlin SoC binding documentation. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*	ARM: dts: berlin: add the Marvell Armada 1500 pro	Antoine Tenart	2014-05-19	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \|	Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family). The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local timer, apb timers and uarts for now. Also add corresponding binding documentation. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*	ARM: add Armada 1500 and Sony NSZ-GS7 device tree files	Sebastian Hesselbarth	2013-12-13	1	-0/+24
	This adds very basic device tree files for the Marvell Armada 1500 SoC (Berlin BG2) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has nodes for cpus, some clocks, l2 cache controller, local timer, apb timers, uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer device comprising the Armada 1500 SoC above. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jisheng Zhang <jszhang@marvell.com>