Commit message (Collapse) | Author | Age | Files | Lines | |
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* | dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset ↵ | Xingyu Wu | 2023-07-19 | 1 | -0/+82 |
generator Add bindings for the System-Top-Group clock and reset generator (STGCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |