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* dt-bindings: PCI: layerscape-pci: Convert to YAML formatFrank Li2024-05-151-79/+0
| | | | | | | | | Convert layerscape PCIe bind document to the preferred YAML format. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20240207231550.2663689-1-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
* dt-bindings: pci: layerscape-pci: define AER/PME interruptsLi Yang2022-04-081-26/+32
| | | | | | | | | | | | | | | | | | | Different platforms using this controller are using different numbers of interrupt lines and the routing of events to these interrupt lines are different too. So instead of trying to define names for these interrupt lines, we define the more specific AER/PME events that are routed to these interrupt lines. For platforms which only has a single interrupt line for miscellaneous controller events, we can keep using the original "intr" name for backward compatibility. Also change the example from ls1021a to ls1088a for better representation. Link: https://lore.kernel.org/r/20220311234938.8706-5-leoyang.li@nxp.com Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
* dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028aXiaowei Bao2022-04-081-0/+1
| | | | | | | | | | | Add EP mode compatible string for ls1028a. Link: https://lore.kernel.org/r/20220311234938.8706-4-leoyang.li@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
* dt-bindings: pci: layerscape-pci: Update the description of SCFG propertyHou Zhiqiang2022-04-081-1/+1
| | | | | | | | | | | Update the description of the second entry of 'fsl,pcie-scfg' property, as the LS1043A PCIe controller also has some control registers in SCFG block, while it has 3 controllers. Link: https://lore.kernel.org/r/20220311234938.8706-3-leoyang.li@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
* dt-bindings: pci: layerscape-pci: Add a optional property big-endianHou Zhiqiang2022-04-081-0/+4
| | | | | | | | | | | This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property. Link: https://lore.kernel.org/r/20220311234938.8706-2-leoyang.li@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
* dt-bindings: PCI: update references to Designware schemaMauro Carvalho Chehab2021-07-191-1/+1
| | | | | | | | | Now that its contents were converted to a DT schema, replace the references for the old file on existing properties. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/dfff4d94631546c53450d1baeddc694dd26b5c36.1626608375.git.mchehab+huawei@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
* dt-bindings: PCI: layerscape: Add LX2160A rev2 compatible stringsHou Zhiqiang2021-02-241-0/+1
| | | | | | | | | | Add PCIe Endpoint mode compatible string "fsl,lx2160ar2-pcie-ep" Link: https://lore.kernel.org/r/20201026051448.1913-1-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
* dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088aXiaowei Bao2020-09-211-0/+2
| | | | | | | | | | Add compatible strings for ls1088a and ls2088a. Link: https://lore.kernel.org/r/20200918080024.13639-6-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
* dt-bindings: pci: layerscape-pci: add compatible strings "fsl, ls1028a-pcie"Xiaowei Bao2019-11-061-0/+1
| | | | | | | | | | Add the PCIe compatible string for LS1028A. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
* dt-bindings: add DT binding for the layerscape PCIe controller with EP modeXiaowei Bao2019-02-211-0/+3
| | | | | | | | | | | Add the documentation for the Device Tree binding for the layerscape PCIe controller with EP mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <minghuan.lian@nxp.com> Reviewed-by: Zhiqiang Hou <zhiqiang.hou@nxp.com> Reviewed-by: Rob Herring <robh+dt@kernel.org>
* dt-bindings: pci: layerscape-pci: removed compatible string "snps,dw-pcie"Hou Zhiqiang2018-12-101-3/+3
| | | | | | | | | | | | | | | Removed the compatible string "snps,dw-pcie", it is for the reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP, so it is not suitable for all platform with designware PCIe controller, and platform vendors have themselves' drivers. The compatible string "snsp,dw-pcie" was added by mistake and it's not matched that time, but it is matched because PCIe drivers has been collected recently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* dt-bindings: pci: layerscape-pci: add compatible strings "fsl,ls1043a-pcie"Hou Zhiqiang2018-12-101-0/+1
| | | | | | | | The PCIe compatible string for LS1043A was lost, so add it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* PCI: layerscape: Add support for ls1012aHou Zhiqiang2017-10-121-0/+1
| | | | | | | | | Add support for ls1012a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
* Merge branch 'pci/trivial' into nextBjorn Helgaas2017-09-071-1/+1
|\ | | | | | | | | | | | | * pci/trivial: PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
| * PCI: Fix typos and whitespace errorsBjorn Helgaas2017-09-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: layerscape: Add support for ls1088aHou Zhiqiang2017-08-301-0/+1
| | | | | | | | | | | | | | Add support for ls1088a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
* | PCI: layerscape: Add support for ls2088aHou Zhiqiang2017-08-301-0/+1
|/ | | | | | | | The ls2088a PCIe controller's register addresses are different from ls2080a, so add a match entry to identify ls2088a PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
* PCI: layerscape: Add LS1046a supportMingkai Hu2016-11-111-0/+1
| | | | | | | | | | Add support for the LS1046a PCIe controller. This device has a different LUT_DBG offset, so add "lut_dbg" to ls_pcie_drvdata to describe this difference. [bhelgaas: changelog, remove now-unused PCIE_LUT_DBG] Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* bindings: PCI: layerscape: Add 'dma-coherent' propertyLiu Gang2016-06-161-0/+4
| | | | | | | | | | | | | | | | Add 'dma-coherent' description for PCI nodes. The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* dts/ls2080a: Update PCIe compatibleMinghuan Lian2016-02-251-1/+1
| | | | | | | | | | The patch adds LS2085a to PCIe compatible to fix the compatibility issue when using firmware with LS2085a compatible property. Signed-off-by: Minghuan Lian <minghuan.lian@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* PCI: layerscape: Add support for LS1043a and LS2080aMinghuan Lian2015-11-021-2/+12
| | | | | | | | | | | | Both LS1043a and LS2080a are based on ARMv8 64-bit architecture and have similar PCIe implementation. LUT is added to controller. Add LS1043a and LS2080a support. [bhelgaas: move unused field removal into separate patch, include DT update] Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> (DT update) Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de> (DT update)
* PCI: layerscape: Add Freescale Layerscape PCIe driverMinghuan Lian2014-11-131-0/+42
Add support for Freescale Layerscape PCIe controller. This driver re-uses the Synopsis DesignWare core code. [bhelgaas: add Kconfig dependency on CONFIG_ARM] Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
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