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* dt-bindings: riscv: fix SiFive l2-cache's cache-setsConor Dooley2022-08-111-1/+5
* dt-bindings: riscv: document cbom-block-sizeHeiko Stuebner2022-07-291-0/+5
* dt-bindings: riscv: microchip: add polarberry compatible stringConor Dooley2022-06-021-0/+1
* dt-bindings: riscv: microchip: document icicle reference designConor Dooley2022-06-021-0/+1
* dt-bindings: Fix phandle-array issues in the idle-states bindingsPalmer Dabbelt2022-04-021-0/+2
* RISC-V CPU Idle SupportPalmer Dabbelt2022-03-311-0/+6
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| * dt-bindings: Add common bindings for ARM and RISC-V idle statesAnup Patel2022-03-101-0/+6
* | MAINTAINERS: sifive: drop Yash ShahKrzysztof Kozlowski2022-02-221-1/+0
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* dt-bindings: riscv: correct e51 and u54-mc CPU bindingsKrzysztof Kozlowski2021-09-211-2/+6
* Merge tag 'riscv-for-linus-5.15-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-09-051-0/+27
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| * dt-bindings: riscv: add starfive jh7100 bindingsDrew Fustini2021-08-041-0/+27
* | dt-bindings: sifive-l2-cache: Fix 'select' matchingRob Herring2021-08-201-4/+4
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* dt-bindings: Drop redundant minItems/maxItemsRob Herring2021-06-211-1/+0
* dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoCAtish Patra2021-04-261-0/+27
* Merge tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-02-264-9/+97
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| * dt-bindings: update risc-v cpu propertiesDamien Le Moal2021-02-231-0/+2
| * dt-bindings: add Canaan boards compatible stringsDamien Le Moal2021-02-231-0/+47
| * dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched boardYash Shah2021-01-081-5/+12
| * dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoCYash Shah2021-01-081-0/+6
| * dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFiv...Yash Shah2021-01-081-4/+30
* | dt-bindings: Add missing array size constraintsRob Herring2021-01-121-0/+1
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* dt-bindings: Explicitly allow additional properties in board/SoC schemasRob Herring2020-10-261-0/+3
* dt-bindings: More whitespace clean-ups in schema filesRob Herring2020-10-261-2/+2
* dt-bindings: Explicitly allow additional properties in common schemasRob Herring2020-10-071-0/+2
* dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schemaSagar Kadam2020-10-012-51/+98
* dt-bindings: Remove cases of 'allOf' containing a '$ref'Rob Herring2020-05-031-11/+9
* dt-bindings: riscv: Fix CPU schema errorsRob Herring2019-10-231-16/+13
* dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed...Paul Walmsley2019-08-091-1/+1
* dt-bindings: riscv: remove obsolete cpus.txtPaul Walmsley2019-08-092-162/+12
* dt-bindings: Update the riscv,isa string descriptionAtish Patra2019-08-091-0/+4
* dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodesRob Herring2019-07-211-82/+61
* dt-bindings: riscv: resolve 'make dt_binding_check' warningsPaul Walmsley2019-06-261-12/+14
* dt-bindings: riscv: convert cpu binding to json-schemaPaul Walmsley2019-06-171-0/+168
* dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540Paul Walmsley2019-06-171-0/+25
* RISC-V: Add DT documentation for SiFive L2 Cache ControllerYash Shah2019-05-171-0/+51
* dt-bindings: RISC-V CPU BindingsPalmer Dabbelt2017-09-261-0/+162
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