Commit message (Expand) | Author | Age | Files | Lines | |
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* | dt-bindings: riscv: Fix CPU schema errors | Rob Herring | 2019-10-23 | 1 | -16/+13 |
* | dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed... | Paul Walmsley | 2019-08-09 | 1 | -1/+1 |
* | dt-bindings: riscv: remove obsolete cpus.txt | Paul Walmsley | 2019-08-09 | 2 | -162/+12 |
* | dt-bindings: Update the riscv,isa string description | Atish Patra | 2019-08-09 | 1 | -0/+4 |
* | dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes | Rob Herring | 2019-07-21 | 1 | -82/+61 |
* | dt-bindings: riscv: resolve 'make dt_binding_check' warnings | Paul Walmsley | 2019-06-26 | 1 | -12/+14 |
* | dt-bindings: riscv: convert cpu binding to json-schema | Paul Walmsley | 2019-06-17 | 1 | -0/+168 |
* | dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 | Paul Walmsley | 2019-06-17 | 1 | -0/+25 |
* | RISC-V: Add DT documentation for SiFive L2 Cache Controller | Yash Shah | 2019-05-17 | 1 | -0/+51 |
* | dt-bindings: RISC-V CPU Bindings | Palmer Dabbelt | 2017-09-26 | 1 | -0/+162 |