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Patch series from Nick Hawkins:
"The GXP is the HPE BMC SoC that is used in the majority of HPE current
generation servers. Traditionally the asic will last multiple
generations of server before being replaced.
Info about SoC:
HPE GXP is the name of the HPE Soc. This SoC is used to implement many
BMC features at HPE. It supports ARMv7 architecture based on the Cortex
A9 core. It is capable of using an AXI bus to which a memory controller
is attached. It has multiple SPI interfaces to connect boot flash and
BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has
multiple i2c engines to drive connectivity with a host infrastructure.
The initial patches enable the watchdog and timer enabling the host to
be able to boot."
* hpe/gxp-soc:
MAINTAINERS: Introduce HPE GXP Architecture
ARM: dts: Introduce HPE GXP Device tree
dt-bindings: arm: hpe: add GXP Support
dt-bindings: timer: hpe,gxp-timer: Add HPE GXP Timer and Watchdog
clocksource/drivers/timer-gxp: Add HPE GXP Timer
watchdog: hpe-wdt: Introduce HPE GXP Watchdog
ARM: configs: multi_v7_defconfig: Add HPE GXP ARCH
ARM: hpe: Introduce the HPE GXP architecture
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add support for HPE GXP. The GXP is based on the cortex a9 processor and
supports arm7.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add support for the HPE GXP Timer and Watchdog. There are multiple
timers on the SoC but only one is enabled at this time.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull asm-generic updates from Arnd Bergmann:
"The asm-generic tree contains three separate changes for linux-5.19:
- The h8300 architecture is retired after it has been effectively
unmaintained for a number of years. This is the last architecture
we supported that has no MMU implementation, but there are still a
few architectures (arm, m68k, riscv, sh and xtensa) that support
CPUs with and without an MMU.
- A series to add a generic ticket spinlock that can be shared by
most architectures with a working cmpxchg or ll/sc type atomic,
including the conversion of riscv, csky and openrisc. This series
is also a prerequisite for the loongarch64 architecture port that
will come as a separate pull request.
- A cleanup of some exported uapi header files to ensure they can be
included from user space without relying on other kernel headers"
* tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
h8300: remove stale bindings and symlink
sparc: add asm/stat.h to UAPI compile-test coverage
powerpc: add asm/stat.h to UAPI compile-test coverage
mips: add asm/stat.h to UAPI compile-test coverage
riscv: add linux/bpf_perf_event.h to UAPI compile-test coverage
kbuild: prevent exported headers from including <stdlib.h>, <stdbool.h>
agpgart.h: do not include <stdlib.h> from exported header
csky: Move to generic ticket-spinlock
RISC-V: Move to queued RW locks
RISC-V: Move to generic spinlocks
openrisc: Move to ticket-spinlock
asm-generic: qrwlock: Document the spinlock fairness requirements
asm-generic: qspinlock: Indicate the use of mixed-size atomics
asm-generic: ticket-lock: New generic ticket-based spinlock
remove the h8300 architecture
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These four files are left over from the h8300 removal.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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asm-generic
* 'remove-h8300' of git://git.infradead.org/users/hch/misc:
remove the h8300 architecture
This is clearly the least actively maintained architecture we have at
the moment, and probably the least useful. It is now the only one that
does not support MMUs at all, and most of the boards only support 4MB
of RAM, out of which the defconfig kernel needs more than half just
for .text/.data.
Guenter Roeck did the original patch to remove the architecture in 2013
after it had already been obsolete for a while, and Yoshinori Sato brought
it back in a much more modern form in 2015. Looking at the git history
since the reinstantiation, it's clear that almost all commits in the tree
are build fixes or cross-architecture cleanups:
$ git log --no-merges --format=%an v4.5.. arch/h8300/ | sort | uniq
-c | sort -rn | head -n 12
25 Masahiro Yamada
18 Christoph Hellwig
14 Mike Rapoport
9 Arnd Bergmann
8 Mark Rutland
7 Peter Zijlstra
6 Kees Cook
6 Ingo Molnar
6 Al Viro
5 Randy Dunlap
4 Yury Norov
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Signed-off-by: Christoph Hellwig <hch@lst.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"There are minor updates to SoC specific drivers for chips by Rockchip,
Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom.
Noteworthy driver changes include:
- Several conversions of DT bindings to yaml format.
- Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
- Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
and support for more chips in the RPMh power domains and the
soc-id.
- NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
- Apple M1 gains support for the on-chip NVMe controller, making it
possible to finally use the internal disks. This also includes SoC
drivers for their RTKit IPC and for the SART DMA address filter.
For other subsystems that merge their drivers through the SoC tree, we
have
- Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
now has a cache for firmware argument structures as an
optimization, and SCMI now supports the 3.1 version of the
specification.
- Reset controller updates to Amlogic, ASpeed, Renesas and ACPI
drivers
- Memory controller updates for Tegra, and a few updates for other
platforms"
* tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits)
memory: tegra: Add MC error logging on Tegra186 onward
memory: tegra: Add memory controller channels support
memory: tegra: Add APE memory clients for Tegra234
memory: tegra: Add Tegra234 support
nvme-apple: fix sparse endianess warnings
soc/tegra: pmc: Document core domain fields
soc: qcom: pdr: use static for servreg_* variables
soc: imx: fix semicolon.cocci warnings
soc: renesas: R-Car V3U is R-Car Gen4
soc: imx: add i.MX8MP HDMI blk-ctrl
soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
soc: imx: add i.MX8MP HSIO blk-ctrl
soc: imx: imx8m-blk-ctrl: set power device name
soc: qcom: llcc: Add sc8180x and sc8280xp configurations
dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
soc/tegra: pmc: Select REGMAP
dt-bindings: reset: st,sti-powerdown: Convert to yaml
dt-bindings: reset: st,sti-picophyreset: Convert to yaml
dt-bindings: reset: socfpga: Convert to yaml
dt-bindings: reset: snps,axs10x-reset: Convert to yaml
...
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers
Powerdomain fixes and improvements, some GRF compatible properties
and a rk3566 GRF clocksource default setup.
* tag 'v5.19-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
soc: rockchip: Fix compile-testing SoC drivers
soc: rockchip: power-domain: Replace dsb() with smb()
soc: rockchip: Clean up Kconfig whitespace
soc: rockchip: set dwc3 clock for rk3566
dt-bindings: soc: rockchip: add rk3566-pipe-grf compatible
soc: rockchip: pm_domains: Fix typo in comment
dt-bindings: soc: rockchip: add naneng combo phy register compatible
Link: https://lore.kernel.org/r/3998951.tdWV9SEqCh@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The rk3566 requires special handling for the dwc3-otg clock in order for
the port to function correctly.
Add a binding for the rk3566-pipe-grf so we can handle setup with the
grf driver.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220408151237.3165046-2-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add Naneng combo phy register compatible.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220324120122.1339-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for v5.19
This converts a wide range of Qualcomm-related DeviceTree bindings to
YAML, in order to improve our ability to validate the DeviceTree source.
The RPMh power-domain driver gains support for the modem platform SDX65,
the compute platform SC8280XP and the automotive platform SA8540p. While
LLCC gains support for SC8180X and SC8280XP and gains a
MODULE_DEVICE_TABLE() to make it functional as a module.
It adds a driver for configuring the SSC bus, providing Linux access to
the hardware blocks in the sensor subsystem.
The socinfo driver gets confusion related to MSM8974 Pro sorted out and
adds new ids for SM8540 and SC7280.
The SCM driver gains support for MSM8974.
Add missing of_node_put() in smp2p and smsm drivers.
Stop using iterator after list_for_each_entry() and define static
definitions as such, in the PDR driver.
* tag 'qcom-drivers-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (33 commits)
soc: qcom: pdr: use static for servreg_* variables
soc: qcom: llcc: Add sc8180x and sc8280xp configurations
dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
soc: qcom: rpmhpd: add sc8280xp & sa8540p rpmh power-domains
soc: qcom: rpmhpd: Don't warn about sparse rpmhpd arrays
dt-bindings: power: rpmpd: Add sc8280xp RPMh power-domains
spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema
soc: qcom: socinfo: Sort out 8974PRO names
dt-bindings: soc: qcom,smp2p: convert to dtschema
dt-bindings: qcom: geni-se: Update UART schema reference
dt-bindings: qcom: geni-se: Update I2C schema reference
dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema
bus: add driver for initializing the SSC bus on (some) qcom SoCs
dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus
dt-bindings: qcom: qcom,geni-se: refer to dtschema for SPI
dt-bindings: soc: qcom,smd: convert to dtschema
firmware: qcom_scm: Add compatible for MSM8976 SoC
dt-bindings: firmware: qcom-scm: Document msm8976 bindings
soc: qcom: smem: validate fields of shared structures
soc: qcom: smem: map only partitions used by local HOST
...
Link: https://lore.kernel.org/r/20220509181839.316655-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add compatibles for the SC8180X and SC8280XP platforms to the existing
LLCC binding.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220502215406.612967-2-bjorn.andersson@linaro.org
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The sc8280xp has 13 power-domains controlled through the RPMh, document
the compatible and provide definitions for the power-domains - and their
active-only variants where applicable.
The SA8540p differs slightly in the power domains exposed, so add a
separate compatible for this, but reuse the constants to allow sharing
the DeviceTree source.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20220426233508.1762345-2-bjorn.andersson@linaro.org
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Convert the GENI based Qualcomm Universal Peripheral (QUP) Serial
Peripheral Interface (SPI) bindings to DT Schema.
The original bindings in TXT were not complete, so add during conversion
properties already used in DTS and/or in the driver: dmas,
interconnects, operating points and power-domains.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220404064017.68634-1-krzysztof.kozlowski@linaro.org
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Convert the Qualcomm Shared Memory Point 2 Point bindings to DT Schema.
Changes against original bindings: enforce only specific names of child
nodes, instead of any names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411155528.502889-1-krzysztof.kozlowski@linaro.org
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We now have geni based QUP UART controller individual binding, update
reference in parent schema and remove properties from common wrapper.
With removal of last child node schema, remove common properties of all
the controllers as they have become obsolete now.
Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220404182938.29492-5-singh.kuldeep87k@gmail.com
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We now have geni based QUP I2C controller binding in place as
dt-bindigs/i2c/qcom,i2c-geni-qcom.yaml similar to other controllers,
update reference in parent schema and while at it, also remove
properties defined for the controller from common wrapper.
Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220404182938.29492-3-singh.kuldeep87k@gmail.com
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Convert the Qualcomm RPMH RSC bindings to DT Schema.
Changes against original bindings:
1. Add qcom,tcs-offset as a property instead of one of reg (not used
that way).
2. Add limits to interrupts.
3. Add child nodes (bcm-voter, clock-controller, power-controller).
4. Extend the example with more complex one.
The device description and DTS examples were copied from existing
sources, so keep the license as GPL-2.0-only.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411085935.130072-4-krzysztof.kozlowski@linaro.org
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Adds bindings for the AHB bus which exposes the SSC block in the global
address space. This bus (and the SSC block itself) is present on certain
qcom SoCs.
In typical configuration, this bus (as some of the clocks and registers
that we need to manipulate) is not accessible to the OS, and the
resources on this bus are indirectly accessed by communicating with a
hexagon CPU core residing in the SSC block. In this configuration, the
hypervisor is the one performing the bus initialization for the purposes
of bringing the haxagon CPU core out of reset.
However, it is possible to change the configuration, in which case this
binding serves to allow the OS to initialize the bus.
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411072156.24451-4-michael.srba@seznam.cz
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After adding DT schema for the SPI controller, the Qualcomm GENI Serial
Engine QUP Wrapper Controller bindings can reference it directly for
full schema validation.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220404064017.68634-2-krzysztof.kozlowski@linaro.org
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Convert the Qualcomm Shared Memory Driver bindings to DT Schema.
Changes against original bindings: enforce only specific names of child
nodes, instead of any names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220401201035.189106-9-krzysztof.kozlowski@linaro.org
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SCM driver on MSM8976 requires 3 clocks.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220307191726.10869-4-a39.skl@gmail.com
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Kathiravan's email bounces (585: Recipient address rejected:
undeliverable address: No such user here) so switch maintainers to Andy
and Bjorn (as Qualcomm platform maintainers).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220401202759.191560-1-krzysztof.kozlowski@linaro.org
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Convert the Qualcomm General Serial Bus Interface (GSBI) to DT
Schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-10-krzysztof.kozlowski@linaro.org
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Convert the Qualcomm WCNSS bindings to DT Schema.
Changes against original bindings: fix qcom,smd-channels and
qcom,smem-states names (how they are used in DTS and driver), enforce
child node naming of bluetooth and wifi.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405065752.27389-3-krzysztof.kozlowski@linaro.org
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Convert the Qualcomm Shared Memory State Machine to DT schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405065512.26521-1-krzysztof.kozlowski@linaro.org
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Add compatibles for the sa8540p automotive, as well as sc8180x and
sc8280xp compute platforms. Also add compatibles for the ADP devboard,
the Lenovo Flex 5G, Microsoft Surface Pro X and the sc8280xp QRD.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220225035415.2294821-1-bjorn.andersson@linaro.org
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Add RPM power domain bindings for the SDX65 SoC.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647410837-22537-4-git-send-email-quic_rohiagar@quicinc.com
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.19:
- A series from Lucas and Paul to update GPCv2 driver for i.MX8MP power
domains, and add HSIO and HDMI block control support.
* tag 'imx-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: fix semicolon.cocci warnings
soc: imx: add i.MX8MP HDMI blk-ctrl
soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
soc: imx: add i.MX8MP HSIO blk-ctrl
dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
dt-bindings: soc: Add i.MX8MP media block control DT bindings
soc: imx: imx8m-blk-ctrl: set power device name
soc: imx: gpcv2: add support for i.MX8MP power domains
soc: imx: gpcv2: add PGC control register indirection
Link: https://lore.kernel.org/r/20220508033843.2773685-2-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers
Samsung SoC drivers changes for v5.19
Make MCT and USI bindings stricter by describing expected interrupts
per variant and expected child node.
* tag 'samsung-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
dt-bindings: timer: exynos4210-mct: describe known hardware and its interrupts
dt-bindings: soc: samsung: usi: refer to dtschema for SPI
Link: https://lore.kernel.org/r/20220506081438.149192-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Most of the Samsung Exynos SoCs use almost the same Multi-Core Timer
block, so only two compatibles were used so far (for Exynos4210 and
Exynos4412 flavors) with Exynos4210-one being used in most of the SoCs.
However the Exynos4210 flavor actually differs by number of interrupts.
Add new compatibles, maintaining backward compatibility with Exynos4210,
and constraints for number of interrupts. This allows to exactly match
the Exynos MCT hardware.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407194127.19004-1-krzysztof.kozlowski@linaro.org
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After adding DT schema for Samsung SPI controller, the Samsung USI
bindings can reference it directly for proper schema validation.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220324134106.103588-1-krzk@kernel.org
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https://github.com/AsahiLinux/linux into arm/drivers
Apple SoC NVMe driver and dependencies:
- RTKit IPC library required to boot and communicate with
co-processors embedded inside Apple SoCs
- SART DMA address filter required to allow some DMA transactions for
the NVMe co-processor
- NVMe platform driver
The following minor changes since v3 on the mailing list have been
folded in:
- sart: %llx -> %pa for a phys_addr_t
- rtkit:/sart: Drop IS_ENABLED inside headers
- rtkit: Use EXPORT_SYMBOL_GPL instead of EXPORT_SYMBOL
- nvme: Set NVME_REQ_CANCELLED in the timeout handler
- nvme: Use DEFINE_SIMPLE_DEV_PM_OPS instead of #ifdef CONFIG_PM_SLEEP
* tag 'asahi-soc-rtkit-sart-nvme-for-5.19' of https://github.com/AsahiLinux/linux:
nvme-apple: Add initial Apple SoC NVMe driver
dt-bindings: nvme: Add Apple ANS NVMe
soc: apple: Add SART driver
dt-bindings: iommu: Add Apple SART DMA address filter
soc: apple: Add RTKit IPC library
soc: apple: Always include Makefile
Link: https://lore.kernel.org/r/20220505154020.84638-1-sven@svenpeter.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Apple SoCs such as the M1 come with an embedded NVMe coprocessor called
ANS2.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
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Apple SoCs such as the M1 come with a simple DMA address filter called
SART. Unlike a real IOMMU no pagetables can be configured but instead
DMA transactions can be allowed for up to 16 paddr regions. The consumer
also needs special support since not all DMA allocations have to be
added to this filter.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
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arm/drivers
Reset controller updates for v5.19
Add Meson-S4 SoC reset controller support to reset-meson, AST2600 LPC
reset controller support to reset-simple, and R9A07G054 USBPHY reset
controller support to reset-rzg2l-usbphy-ctrl. Add ACPI _RST support to
device_reset(), simplify the uniphier-glue reset driver using bulk API
and devres and clean up its dt-bindings docs. Convert most dt-bindings
docs from txt to yaml.
* tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux:
dt-bindings: reset: st,sti-powerdown: Convert to yaml
dt-bindings: reset: st,sti-picophyreset: Convert to yaml
dt-bindings: reset: socfpga: Convert to yaml
dt-bindings: reset: snps,axs10x-reset: Convert to yaml
dt-bindings: reset: nuvoton,npcm-reset: Convert to yaml
dt-bindings: reset: lantiq,reset: Convert to yaml
dt-bindings: reset: bitmain,bm1880-reset: Convert to yaml
dt-bindings: reset: berlin: Convert to yaml
dt-bindings: reset: ath79: Convert to yaml
dt-bindings: reset: amlogic,meson-axg-audio-arb: Convert to yaml
dt-bindings: reset: uniphier-glue: Clean up clocks, resets, and their names using compatible string
reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L
reset: ACPI reset support
reset: simple: Add AST2600 compatible
reset: reset-meson: add support for the Meson-S4 SoC Reset Controller
dt-bindings: reset: add bindings for the Meson-S4 SoC Reset Controller
dt-bindings: reset: Add compatible for Meson-S4 Reset Controller
reset: uniphier-glue: Use devm_add_action_or_reset()
reset: uniphier-glue: Use reset_control_bulk API
Link: https://lore.kernel.org/r/20220503160057.46625-1-p.zabel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Convert the device tree bindings for the STMicroelectronics STi
Peripheral Powerdown reset controller to YAML schema to allow
participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-13-p.zabel@pengutronix.de
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Convert the device tree bindings for the STMicroelectronics STi
SoftReset controller to YAML schema to allow participating in DT
validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-12-p.zabel@pengutronix.de
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Convert the device tree bindings for the Altera SOCFPGA reset manager to
YAML schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-11-p.zabel@pengutronix.de
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Convert the device tree bindings for the AXS10x reset controller to YAML
schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-8-p.zabel@pengutronix.de
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Convert the device tree bindings for the Nuvoton NPCM reset controller
to YAML schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Avi Fishman <avifishman70@gmail.com>
Cc: Tomer Maimon <tmaimon77@gmail.com>
Cc: Tali Perry <tali.perry1@gmail.com>
Cc: Patrick Venture <venture@google.com>
Cc: Nancy Yuen <yuenn@google.com>
Cc: Benjamin Fair <benjaminfair@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-6-p.zabel@pengutronix.de
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Convert the device tree bindings for the Lantiq XWAY SoC RCU reset
controller to YAML schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-5-p.zabel@pengutronix.de
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Convert the device tree bindings for the Bitmain BM1880 reset controller
to YAML schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-4-p.zabel@pengutronix.de
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Convert the device tree bindings for the Marvell Berlin reset controller
to YAML schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Antoine Tenart <atenart@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-3-p.zabel@pengutronix.de
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Convert the device tree bindings for the Qualcomm Atheros AR7xxx/AR9XXX
reset controller to YAML schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Alban Bedel <albeu@free.fr>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-2-p.zabel@pengutronix.de
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Convert the device tree bindings for the Amlogic audio memory arbiter
controller to YAML schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-1-p.zabel@pengutronix.de
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using compatible string
Instead of "oneOf:" choices, use "allOf:" and "if:" to define clocks,
resets, and their names that can be taken by the compatible string.
The order of clock-names and reset-names doesn't change here.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/1649145378-30358-1-git-send-email-hayashi.kunihiko@socionext.com
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Add new compatible for Amlogic's Meson-S4 Reset Controller
Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20220107023931.13251-2-zelong.dong@amlogic.com
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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.19
1. Exynos: Reduce memory usage/allocation in Exynos5422 DMC driver.
2. Renesas:
- Add bindings for R-Car H3/M3/E3.
- Simplify single/double data register access.
3. Minor cleanups: TI/EMIF and FSL/Corenet.
* tag 'memory-controller-drv-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: fsl-corenet-cf: Use helper function devm_platform_ioremap_resource()
memory: renesas-rpc-if: Simplify single/double data register access
dt-bindings: memory: renesas,rpc-if: Document R-Car H3/M3/E3 support
memory: emif: remove unneeded ENOMEM error messages
memory: samsung: exynos5422-dmc: Avoid some over memory allocation
Link: https://lore.kernel.org/r/20220420072712.12648-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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