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2013-10-11drm/i915: Fix VLV frame counter registersVille Syrjälä1-8/+8
2013-10-11drm/i915/vlv: add doc names to sideband fileJesse Barnes1-1/+4
2013-10-11drm/i915: don't save/restore CACHE_MODE_0 on gen7+Jesse Barnes1-2/+5
2013-10-11drm/i915: Fix pipe off timeout handling for pre-gen4Ville Syrjälä1-15/+20
2013-10-11drm/i915: increase the SWSCI DSLP default timeout to 50msPaulo Zanoni1-1/+3
2013-10-10drm/i915: Avoid tweaking RPS before it is enabledChris Wilson2-10/+17
2013-10-10drm/i915: tell the user KMS is required for gen6+Jani Nikula1-1/+4
2013-10-10drm/i915: Educate users in dmesg about reporting gpu hangsDaniel Vetter1-2/+6
2013-10-10drm/i915: Finish enabling rps before use by sysfs or debugfsTom O'Rourke2-0/+22
2013-10-10drm/i915: Capture the initial error-state when kicking stuck ringsChris Wilson1-0/+2
2013-10-10drm/i915: Rename primary_disabled to primary_enabledVille Syrjälä4-11/+11
2013-10-10drm/i915: Populate primary_disabled in intel_modeset_readout_hw_state()Ville Syrjälä1-0/+1
2013-10-10drm/i915: don't leak dp_connector at intel_ddi_initPaulo Zanoni1-20/+42
2013-10-10drm/i915/dp: update training set in a burst write with training pattern setJani Nikula1-14/+14
2013-10-10drm/i915: Do PCH and uncore init earlierBen Widawsky1-4/+6
2013-10-10drm/i915: wait for IPS_ENABLE when enabling IPSPaulo Zanoni1-0/+8
2013-10-10drm/i915: Keep intel_drv.h tidyDaniel Vetter1-3/+2
2013-10-10drm/i915: Remove gen specific checks in MMIOBen Widawsky4-18/+12
2013-10-10drm/i915: Create GEN specific write MMIOBen Widawsky1-13/+74
2013-10-10drm/i915: Create GEN specific read MMIOBen Widawsky1-13/+59
2013-10-10drm/i915: Extract common MMIO linesBen Widawsky1-9/+21
2013-10-10drm/i915: Create MMIO virtual functionsBen Widawsky2-95/+104
2013-10-10drm/i915: Move edram detection early_sanitizeBen Widawsky2-10/+11
2013-10-10drm/i915: Prevent using uninitialized MMIO funcsBen Widawsky1-1/+1
2013-10-10drm/i915: rip out gen2 reset codeDaniel Vetter1-31/+0
2013-10-10drm/i915: check that the i965g/gm 4G limit is really obeyedDaniel Vetter1-0/+3
2013-10-10drm/i915: Undo the PIPEA quirk for i845Chris Wilson1-2/+1
2013-10-10drm/i915: Use the real cpu max frequency for ring scalingBen Widawsky1-6/+11
2013-10-10drm/i915: Flush primary plane changes in sprite codeVille Syrjälä1-0/+2
2013-10-10drm/i915: WARN if primary plane state doesn't match expectationsVille Syrjälä1-0/+4
2013-10-10drm/i915: Rename intel_{enable, disable}_plane to intel_{enable, disable}_pri...Ville Syrjälä1-13/+13
2013-10-10drm/i915: Rename intel_flush_display_plane to intel_flush_primary_planeVille Syrjälä4-12/+12
2013-10-10drm/i915: Enable/disable IPS when primary is enabled/disabledVille Syrjälä3-2/+23
2013-10-10drm/i915: Do the fbc vs. primary plane enable/disable in the right orderVille Syrjälä1-5/+6
2013-10-10drm/i915: Save user requested plane coordinates only on successVille Syrjälä1-9/+22
2013-10-10drm/i915: Do a bit of cleanup in the sprite codeVille Syrjälä1-9/+5
2013-10-10drm/i915: Kill a goto from sprite disable codeVille Syrjälä1-12/+9
2013-10-10drm/i915: Reduce the time we hold struct mutex in sprite update_plane codeVille Syrjälä1-11/+18
2013-10-10drm/i915: Allow sprites to be configured on a disabled pipeVille Syrjälä1-33/+32
2013-10-10drm/i915: Set primary_disabled in intel_{enable, disable}_planeVille Syrjälä1-0/+8
2013-10-10drm/i915/dp: promote clock recovery failures to DRM_ERRORJani Nikula1-2/+2
2013-10-10drm/i915: Fix VGA_DISP_DISABLE checkVille Syrjälä1-1/+1
2013-10-10drm/i915: Use intel_PLL_is_valid() in vlv_find_best_dpll()Ville Syrjälä1-11/+24
2013-10-10drm/i915: Don't lie about findind suitable PLL settings on VLVVille Syrjälä1-1/+4
2013-10-10drm/i915: intel_limits_vlv_dac and intel_limits_vlv_hdmi are the sameVille Syrjälä1-15/+2
2013-10-10drm/i915: Remove unused dot_limit from VLV PLL limitsVille Syrjälä1-4/+2
2013-10-10drm/i915: Remove the unused p and m limits for VLVVille Syrjälä1-4/+0
2013-10-10drm/i915: Respect p2 divider minimum limit on VLVVille Syrjälä1-3/+3
2013-10-10drm/i915: Allow p1 divider 2 on VLVVille Syrjälä1-1/+1
2013-10-10drm/i915: Clarify VLV PLL p1 limitsVille Syrjälä1-3/+3
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