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2024-03-20ACPI: Enable ACPI_PROCESSOR for RISC-VSunil V L1-1/+1
2024-03-20ACPI: RISC-V: Add LPI driverSunil V L2-1/+83
2024-03-20cpuidle: RISC-V: Move few functions to arch/riscvSunil V L3-44/+57
2024-03-20riscv: Introduce set_compat_task() in asm/compat.hLeonardo Bras2-4/+9
2024-03-20riscv: Introduce is_compat_thread() into compat.hLeonardo Bras2-3/+11
2024-03-20riscv: add compile-time test into is_compat_task()Leonardo Bras4-12/+5
2024-03-20riscv: Replace direct thread flag check with is_compat_task()Leonardo Bras2-2/+2
2024-03-20riscv: Improve arch_get_mmap_end() macroLeonardo Bras1-3/+9
2024-03-15riscv: vector: Fix a typo of preempt_vSong Shuai1-2/+2
2024-03-15riscv: Fix compilation error with FAST_GUP and rv32Alexandre Ghiti1-0/+2
2024-03-14docs: riscv: Define behavior of mmapCharlie Jenkins1-11/+5
2024-03-14selftests: riscv: Generalize mm selftestsCharlie Jenkins3-86/+67
2024-03-14riscv: mm: Use hint address in mmap if availableCharlie Jenkins1-16/+11
2024-03-13riscv: Set unaligned access speed at compile timeCharlie Jenkins7-296/+359
2024-03-13riscv: Decouple emulated unaligned accesses from access speedCharlie Jenkins3-13/+29
2024-03-13riscv: Only check online cpus for emulated accessesCharlie Jenkins1-1/+1
2024-03-13riscv: lib: Introduce has_fast_unaligned_access()Charlie Jenkins3-11/+13
2024-03-12riscv: andes: Support specifying symbolic firmware and hardware raw eventsLocus Wei-Han Chen5-0/+330
2024-03-12riscv: dts: renesas: Add Andes PMU extension for r9a07g043fYu Chien Peter Lin1-1/+1
2024-03-12dt-bindings: riscv: Add Andes PMU extension descriptionYu Chien Peter Lin1-0/+7
2024-03-12perf: RISC-V: Introduce Andes PMU to support perf event samplingYu Chien Peter Lin5-12/+48
2024-03-12perf: RISC-V: Eliminate redundant interrupt enable/disable operationsYu Chien Peter Lin1-2/+0
2024-03-12riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTCYu Chien Peter Lin1-1/+1
2024-03-12dt-bindings: riscv: Add Andes interrupt controller compatible stringYu Chien Peter Lin1-1/+5
2024-03-12riscv: errata: Rename defines for AndesYu Chien Peter Lin4-9/+9
2024-02-29riscv: Fix pte_leaf_size() for NAPOTAlexandre Ghiti1-0/+4
2024-02-29Revert "riscv: mm: support Svnapot in huge vmap"Alexandre Ghiti1-60/+1
2024-02-28RISC-V: fix check for zvkb with tip-of-tree clangEric Biggers1-1/+1
2024-02-23irqchip/riscv-intc: Introduce Andes hart-level interrupt controllerYu Chien Peter Lin2-7/+69
2024-02-23irqchip/riscv-intc: Allow large non-standard interrupt numberYu Chien Peter Lin1-7/+19
2024-02-17RISC-V: Drop invalid test from CONFIG_AS_HAS_OPTION_ARCHNathan Chancellor1-1/+0
2024-02-17kbuild: Add -Wa,--fatal-warnings to as-instr invocationNathan Chancellor2-2/+2
2024-02-16riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520Drew Fustini1-0/+2
2024-02-15membarrier: riscv: Provide core serializing commandAndrea Parri7-1/+77
2024-02-15locking: Introduce prepare_sync_core_cmd()Andrea Parri3-1/+19
2024-02-15membarrier: Create Documentation/scheduler/membarrier.rstAndrea Parri5-5/+51
2024-02-15membarrier: riscv: Add full memory barrier in switch_mm()Andrea Parri5-3/+38
2024-01-25riscv: Avoid code duplication with generic bitops implementationXiao Wang5-122/+48
2024-01-25riscv: Support RANDOMIZE_KSTACK_OFFSETSong Shuai2-1/+17
2024-01-25RISC-V: Remove duplicated include in smpboot.cYang Li1-1/+0
2024-01-25riscv: blacklist assembly symbols for kprobeClément Léger2-0/+13
2024-01-25riscv: enable HAVE_FAST_GUP if MMUJisheng Zhang2-0/+7
2024-01-25riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMUJisheng Zhang3-5/+37
2024-01-25riscv: tlb: convert __p*d_free_tlb() to inline functionsJisheng Zhang1-22/+32
2024-01-25riscv: tlb: fix __p*d_free_tlb()Jisheng Zhang1-3/+17
2024-01-24riscv: mm: Update mmap_rnd_bits_maxSami Tolvanen1-0/+6
2024-01-24mm: Change mmap_rnd_bits_max to __ro_after_initSami Tolvanen2-2/+2
2024-01-23Revert "RISC-V: mark hibernation as nonportable"Conor Dooley1-4/+1
2024-01-23clocksource: extend the max_delta_ns of timer-riscv and timer-clint to ULONG_MAXVincent Chen2-2/+2
2024-01-23crypto: riscv - add vector crypto accelerated SM4Jerry Shih4-0/+244