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path: root/arch/arc/include/asm/arcregs.h (follow)
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
* ARC: boot log: cut down on verbosityVineet Gupta2019-02-261-9/+0
* ARCv2: boot log: refurbish HS core/release identificationVineet Gupta2019-02-261-1/+1
* ARCv2: Add explcit unaligned access support (and ability to disable too)Eugeniy Paltsev2019-02-251-0/+1
* ARCv2: don't assume core 0x54 has dual issueVineet Gupta2019-02-211-0/+8
* ARC: boot log: print Action point detailsVineet Gupta2019-01-171-1/+9
* ARCv2: boot log: BPU return stack depthVineet Gupta2019-01-171-1/+1
* ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop BufferVineet Gupta2017-11-131-1/+32
* ARCv2: boot log: identify HS48 cores (dual issue)Vineet Gupta2017-10-041-1/+2
* ARC: boot log: decontaminate ARCv2 ISA_CONFIG registerVineet Gupta2017-10-041-4/+4
* ARCv2: intc: Use ARC_REG_STATUS32 for addressing STATUS32 regYuriy Kolerov2017-02-061-0/+3
* ARC: mm: No need to save cache version in @cpuinfoVineet Gupta2016-12-191-1/+1
* ARC: breakout timer include code into separate header ...Vineet Gupta2016-11-301-8/+1
* ARC: breakout aux handling into a separate headerVineet Gupta2016-11-301-84/+1
* ARC: change return value of userspace cmpxchg assist syscallVineet Gupta2016-11-071-0/+2
* ARC: boot log: refactor cpu name/release printingVineet Gupta2016-10-281-1/+1
* ARC: boot log: don't assume SWAPE instruction supportVineet Gupta2016-10-281-1/+1
* ARC: boot log: refactor printing abt features not captured in BCRsVineet Gupta2016-10-281-0/+1
* ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 coresVineet Gupta2016-09-301-9/+1
* ARC: build: Better way to detect ISA compatible toolchainVineet Gupta2016-03-121-6/+0
* ARCv2: boot report CCMs (Closely Coupled Memories)Vineet Gupta2016-02-181-12/+20
* ARC: shrink cpuinfo by not saving full timer BCRVineet Gupta2016-01-291-2/+1
* ARC: boot log: decode more mmu config itemsVineet Gupta2015-10-171-1/+1
* ARC: mm: compute TLB size as needed from ways * setsVineet Gupta2015-10-171-2/+2
* ARC: make write_aux_reg safer against macro substitutionVineet Gupta2015-10-171-1/+1
* ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin2015-08-201-0/+1
* ARCv2: Fix the peripheral address space detectionVineet Gupta2015-08-031-4/+3
* ARCv2: MMUv4: cache programming model changesVineet Gupta2015-06-221-2/+3
* ARCv2: MMUv4: TLB programming Model changesVineet Gupta2015-06-221-1/+1
* ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta2015-06-221-4/+49
* ARCv2: [intc] HS38 core interrupt controllerVineet Gupta2015-06-221-0/+1
* ARC: uncached base is hard constant for ARC, don't save itVineet Gupta2015-06-221-1/+0
* ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}Vineet Gupta2015-06-191-3/+0
* ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)Vineet Gupta2015-06-191-1/+2
* ARC: Fix RTT boot printingVineet Gupta2015-04-131-0/+1
* ARC: cosmetic: Remove unused ECR bitfield masksVineet Gupta2015-04-131-6/+3
* ARC: Fix WRITE_BCRVineet Gupta2015-04-131-2/+2
* ARC: boot: cpu feature print enhancementsVineet Gupta2014-10-131-24/+53
* ARC: unbork FPU save/restoreVineet Gupta2014-10-131-8/+0
* ARC: remove extraneous __KERNEL__ guardsVineet Gupta2014-10-131-4/+0
* ARC: cache boot reporting updatesVineet Gupta2014-07-231-1/+1
* ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth valuesVineet Gupta2013-06-261-0/+4
* ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR valuesVineet Gupta2013-06-221-0/+5
* ARC: cache detection code bitrotVineet Gupta2013-06-221-1/+1
* ARC: Disintegrate arcregs.hVineet Gupta2013-06-221-116/+0
* ARC: Boot #2: Verbose Boot reporting / feature verificationVineet Gupta2013-02-151-10/+112
* ARC: Boot #1: low-level, setup_arch(), /proc/cpuinfo, mem initVineet Gupta2013-02-151-0/+5
* ARC: MMU Exception HandlingVineet Gupta2013-02-151-0/+91
* ARC: MMU Context ManagementVineet Gupta2013-02-151-0/+7
* ARC: Cache Flush ManagementVineet Gupta2013-02-151-0/+80
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