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* ARM: dts: Move .dts files to vendor sub-directoriesRob Herring2023-06-211-141/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
* ARM: dts: broadcom: add missing cache propertiesKrzysztof Kozlowski2023-05-081-0/+1
| | | | | | | | | | | | As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: bcm963148.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230423150943.118576-1-krzysztof.kozlowski@linaro.org Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: broadcom: bcmbca: Add spi controller nodeWilliam Zhang2023-03-141-0/+19
| | | | | | | | Add support for HSSPI controller in ARMv7 chip dts files. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230207065826.285013-4-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* arm: dts: Update cache properties for broadcomPierre Gondois2022-11-291-0/+1
| | | | | | | | | | | | | | The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Link: https://lore.kernel.org/r/20221122163208.3810985-2-pierre.gondois@arm.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: bcmbca: bcm63178: cosmetic changeWilliam Zhang2022-08-151-0/+2
| | | | | | | | Add new line between dts node. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20220801194448.29363-4-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: bcmbca: bcm63178: fix interrupt controller nodeWilliam Zhang2022-08-151-3/+5
| | | | | | | | | Add the missing gic registers and interrupts property to the gic node. Fixes: fc85b7e64acb ("ARM: dts: add dts files for bcmbca soc 63178") Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20220801194448.29363-3-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: bcmbca: bcm63178: clean up psci nodeWilliam Zhang2022-08-151-2/+0
| | | | | | | | | | Remove unnecessary cpu_on and cpu_off properties from psci node as they are only needed for psci version prior to 0.2. Fixes: fc85b7e64acb ("ARM: dts: add dts files for bcmbca soc 63178") Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20220801194448.29363-2-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: bcmbca: bcm63178: fix timer node cpu mask flagWilliam Zhang2022-08-151-4/+4
| | | | | | | | | | The cpu mask flag value should match the number of cpu cores in the chip. Correct the value to three cpus for BCM63178 triple core SoC. Fixes: fc85b7e64acb ("ARM: dts: add dts files for bcmbca soc 63178") Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20220801194448.29363-1-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: add dts files for bcmbca soc 63178Anand Gore2022-06-081-0/+118
Add dts for ARMv7 based broadband SoC BCM63178. bcm63178.dtsi is the SoC description dts header and bcm963178.dts is a simple dts file for Broadcom BCM963178 Reference board that only enable the UART port. Signed-off-by: Anand Gore <anand.gore@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>