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* ARM: dts: Move .dts files to vendor sub-directoriesRob Herring2023-06-211-1846/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
* ARM: dts: stm32: add vrefint support to adc2 on stm32mp15Olivier Moysan2023-06-021-0/+2
| | | | | | | | | | | | | | | | Set STM32 ADC2 as a consumer of BSEC on STM32MP15, to retrieve vrefint calibration data saved in OTP. During the calibration process vrefp is set to 3.3V and the data acquired is saved to the OTP. This data is used by the ADC driver to calculated the actual value of vrefp according to the formula: vrefp = 3.3 x vrefint_cal / vrefint_data The vrefint channel provides the actual value of vrefp, which can be used to correct ADC acquisition data. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: add vrefint calibration on stm32mp15Olivier Moysan2023-06-021-0/+3
| | | | | | | Describe vrefint calibration cell to be retrieved through bsec. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: add adc internal channels to stm32mp15Olivier Moysan2023-06-021-0/+12
| | | | | | | | | | | | | | | | | Add STM32 ADC2 internal channels VREFINT and VDDCORE to STM32MP15x SoCs. VBAT internal channel is not defined by default in SoC DT, and has be defined in board DT when needed, instead. This avoids unwanted current consumption on battery, when ADC conversions are performed on any other channels. The internal channels are defined in STM32MP15 SoC DT according to the generic IIO channel bindings. The STM32 driver does not support a mixed use of legacy and generic channels. When generic channels are defined, legacy channels are ignored. This involves that the board device trees using legacy bindings for ADC2, have to be reworked. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: fix ltdc warnings in stm32mp15 boardsRaphael Gallais-Pou2023-05-301-5/+0
| | | | | | | | | | | Those concern: * "#size-cells" and "#address-cells" wrongly used * residual "reg" property appearing on endpoints where it could be avoided Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: Update Cortex-M4 reset declarations on stm32mp15Arnaud Pouliquen2023-05-171-1/+1
| | | | | | | | | | | | | Since the introduction of the SCMI for the management of the MCU hold boot in OP-TEE, management of the hold boot by SMC call is deprecated. - Clean the st,syscfg-tz which allows to determine if the trust zone is enable. - Add reset-names properties to be able to differentiate the MCU reset and the MCU HOLD BOOT. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: add part number for STM32MP15xPatrick Delaunay2023-05-161-0/+3
| | | | | | | | The STM32MP15x Device Part Number is located in the first 8 bits of OTP4, this patch add its description as the NVMEM cell. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: add USB OTG UTMI clock on stm32mp151Fabrice Gasnier2023-04-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It's needed on STM32MP15, when using the integrated full-speed PHY. This clock is an output of USBPHYC, and the HS USBPHYC is not attached as PHY in this case (managed directly by dwc2 ggpio glue): &usbotg_hs { compatible = "st,stm32mp15-fsotg", "snps,dwc2"; pinctrl-names = "default"; pinctrl-0 = <&usbotg_hs_pins_a &usbotg_fs_dp_dm_pins_a>; vbus-supply = <&vbus_otg>; status = "okay"; }; USBPHYC clock output must be used, so it can be properly enabled as a clock provider. Without this, currently, when the dualport High-Speed USBPHYC isn't requested by either USBH or OTG, it remains uninitialized when probing OTG: OTG configured with full-speed PHY isn't properly clocked, resulting in error log like: [ 2.383138] dwc2 49000000.usb-otg: dwc2_core_reset: HANG! Soft Reset timeout GRSTCTL_CSFTRST. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20230414084137.1050487-5-fabrice.gasnier@foss.st.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: dts: stm32: Remove the pins-are-numbered propertyBernhard Rosenkränzer2023-01-171-2/+0
| | | | | | | | Remove the pins-are-numbered property from STM32 DeviceTrees Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: Drop MMCI interrupt-namesMarek Vasut2022-10-241-3/+0
| | | | | | | | | | | The pl18x MMCI driver does not use the interrupt-names property, the binding document has been updated to recommend this property be unused, remove it. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Yann Gautier <yann.gautier@foss.st.com> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: Add timer interrupts on stm32mp15Uwe Kleine-König2022-09-121-0/+34
| | | | | | | | | The timer units in the stm32mp15x CPUs have interrupts, depending on the timer flavour either one "global" or four dedicated ones. Add the irqs to the timer units on stm32mp15x. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151Fabien Dessenne2022-07-051-4/+3
| | | | | | | | | | The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so remove the unsupported "wakeup" one. Note that the EXTI interrupt 61 has two roles : it is hierarchically linked to the GIC IPCC "rx" interrupt, and it acts as a wakeup source. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15Fabrice Gasnier2022-07-041-2/+2
| | | | | | | | | | | | | | | | The USBH composed of EHCI and OHCI controllers needs the PHY clock to be initialized first, before enabling (gating) them. The reverse is also required when going to suspend. So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL gets enabled 1st upon controller init. Upon suspend/resume, this also makes the clock to be disabled/re-enabled in the correct order. This fixes some IRQ storm conditions seen when going to low-power, due to PHY PLL being disabled before all clocks are cleanly gated. Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c") Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: use the correct clock source for CEC on stm32mp151Gabriel Fernandez2022-07-041-1/+1
| | | | | | | The peripheral clock of CEC is not LSE but CEC. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15Alexandre Torgue2022-06-141-41/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding a "secure" version of STM32 boards (DK1/DK2/ED1/EV1), SCMI (clock/ reset) protocol and OP-TEE node have been added in SoC dtsi file (stm32mp151.dtsi). They have been added with a status disabled in order to keep our legacy unchanged. It is actually not enough to keep our legacy unchanged. First, just a reminder about our use case: TF-A (BL2) loads and starts OP-TEE, then loads and runs U-Boot. U-Boot code checks if an OP-TEE is running, if yes it searches in Kernel device tree if an OP-TEE node is present: -If the OP-TEE node is not present then U-Boot copies OP-TEE node and its reserved memory region from U-Boot device tree to the kernel device tree. -If the OP-TEE node is present then it does nothing (this OP-TEE node will be used by Linux). So U-Boot lets the kernel device tree unchanged thinking it is correct for an OP-TEE usage. It is the case for our legacy boards, the OP-TEE node is present (although disabled) but the reserved memory region is not declared. As no memory region has been reserved for OP-TEE, the end of DDR is seen by the kernel as free and then used for CMA. But as OP-TEE is running, this end of DDR is already used by OP-TEE. So as soon as kernel tries to access to the CMA region OP-TEE raises an error. To fix it, all OP-TEE node and SCMI is moved in a dedicated file. Fixes: 40b4157dbd8c ("ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15") Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Link: https://lore.kernel.org/r/20220613071920.5463-1-alexandre.torgue@foss.st.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15Alexandre Torgue2022-05-041-0/+41
| | | | | | Enable optee and SCMI clocks/reset protocols support. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: fix pinctrl node name warnings (MPU soc)Fabien Dessenne2022-04-191-2/+2
| | | | | | | | | The recent addition pinctrl.yaml in commit c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml") resulted in some node name warnings. Fix the node names to the preferred 'pinctrl'. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15Alexandre Torgue2022-02-251-4/+4
| | | | | | | | | Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP151 is a single A7. STM32MP153/157 is a dual A7. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Marc Zyngier <maz@kernel.org>
* ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151Erwan Le Ray2022-02-251-0/+21
| | | | | | | | | | | | | | | | | | | | Add DMA configuration in stm32mp15x uart nodes by selecting dma direct mode and alternate REQ/ACK dma protocol for uart. DMA direct mode allows to bypass DMA FIFO. Each DMA request immediately initiates a transfer from/to the memory. This allows USART to get data transferred, even when the transfer ends before the DMA FIFO completion. Default REQ/ACK DMA protocol consists in maintaining ACK signal up to the removal of REQuest and the transfer completion. In case of alternative REQ/ACK protocol, ACK de-assertion does not wait the removal of the REQuest, but only the transfer completion. Due to a possible DMA stream lock when transferring data to/from STM32 USART/UART, select this alternative protocol in STM32 USART/UART nodes. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on ↵Alexandre Torgue2022-02-251-1/+1
| | | | | | | | | | | stm32mp157 Link between GIC and exti line is now done inside EXTI driver. So in order to be wake up source exti irqchip has to be used. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151Yann Gautier2022-02-071-3/+3
| | | | | | | | | | | | To align with bootloaders device tree files, and thanks to what was added in yaml file [1], the compatible property for sdmmc nodes is updated with "st,stm32-sdmmc2" string. [1] commit 552bc46484b3 ("dt-bindings: mmc: mmci: Add st,stm32-sdmmc2 compatible") Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* Merge tag 'usb-5.16-rc1' of ↵Linus Torvalds2021-11-041-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB / Thunderbolt updates from Greg KH: "Here is the big set of USB and Thunderbolt driver updates for 5.16-rc1. Nothing major in here, just lots of little cleanups and additions for new hardware, all of which have been in linux-next for a while with no reported problems. Included in here are: - tiny Thunderbolt driver updates - USB typec driver updates - USB serial driver updates - USB gadget driver updates - dwc2 and dwc3 controller driver updates - tiny USB host driver updates - minor USB driver fixes and updates - USB dts updates for various platforms" * tag 'usb-5.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (123 commits) usb: gadget: Mark USB_FSL_QE broken on 64-bit usb: gadget: f_mass_storage: Disable eps during disconnect usb: gadget: udc: core: Revise comments for USB ep enable/disable USB: serial: keyspan: fix memleak on probe errors USB: serial: cp210x: use usb_control_msg_recv() and usb_control_msg_send() USB: serial: ch314: use usb_control_msg_recv() USB: iowarrior: fix control-message timeouts Documentation: USB: fix example bulk-message timeout usb: dwc2: stm32mp15: set otg_rev usb: dwc2: add otg_rev and otg_caps information for gadget driver dt-bindings: usb: dwc2: adopt otg properties defined in usb-drd.yaml dt-bindings: usb: dwc2: Add reference to usb-drd.yaml usb: gadget: uvc: implement dwPresentationTime and scrSourceClock usb: gadget: uvc: use on returned header len in video_encode_isoc_sg usb:gadget: f_uac1: fixed sync playback Docs: usb: remove :c:func: for usb_register and usb_deregister Docs: usb: update struct usb_driver usb: gadget: configfs: change config attributes file operation usb: gadget: configfs: add cfg_to_gadget_info() helper usb: dwc3: Align DWC3_EP_* flag macros ...
| * ARM: dts: stm32: set otg-rev on stm32mp151Fabrice Gasnier2021-10-061-0/+1
| | | | | | | | | | | | | | | | STM32MP151 complies with the OTG 2.0. Set it with otg-rev dt property. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/1631692473-8732-4-git-send-email-fabrice.gasnier@foss.st.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151Amelie Delaunay2021-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Referring to the note under USBH reset and clocks chapter of RM0436, "In order to access USBH_OHCI registers it is necessary to activate the USB clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m). The point is, when USBPHYC PLL is not enabled, OHCI register access freezes the resume from STANDBY. It is the case when dual USBH is enabled, instead of OTG + single USBH. When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL is enabled and OHCI register access is OK. This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* | ARM: dts: stm32: fix SAI sub nodes register rangeOlivier Moysan2021-10-151-8/+8
|/ | | | | | | | | | | | The STM32 SAI subblocks registers offsets are in the range 0x0004 (SAIx_CR1) to 0x0020 (SAIx_DR). The corresponding range length is 0x20 instead of 0x1c. Change reg property accordingly. Fixes: 5afd65c3a060 ("ARM: dts: stm32: add sai support on stm32mp157c") Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15Alexandre Torgue2021-06-101-6/+6
| | | | | | | | | It fixes the following warning seen running "make dtbs_check W=1" Warning (simple_bus_reg): /soc/stmmac-axi-config: missing or empty reg/ranges property Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151Patrice Chotard2021-06-011-2/+2
| | | | | | | | | | | | | Configure qspi's mdma from buffer transfer (max 128 bytes) to block transfer (max 64K bytes). mtd_speedtest shows that write throughtput increases : - from 734 to 782 KiB/s (~6.5%) with s25fl512s SPI-NOR. - from 4848 to 5319 KiB/s (~9.72%) with Micron SPI-NAND. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* Merge tag 'arm-dt-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2021-04-261-0/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM devicetree updates from Arnd Bergmann: "There are six new SoCs added this time. Apple M1 and Nuvoton WPCM450 have separate branches because they are new SoC families that require changes outside of device tree files. The other four are variations of already supported chips and get merged through this branch: - STMicroelectronics STM32H750 is one of many variants of STM32 microcontrollers based on the Cortex-M7 core. This is particularly notable since we rarely add support for new MMU-less chips these days. In this case, the board that gets added along with the platform is not a SoC reference platform but the "Art Pi" (https://art-pi.gitee.io/website/) machine that was originally design for the RT-Thread RTOS. - NXP i.MX8QuadMax is a variant of the growing i.MX8 embedded/industrial SoC family, using two Cortex-A72 and four Cortex-A53 cores. It gets added along with its reference board, the "NXP i.MX8QuadMax Multisensory Enablement Kit". - Qualcomm SC7280 is a Laptop SoC following the SC7180 (Snapdragon 7c) that is used in some Chromebooks and Windows laptops. Only a reference board is added for the moment. - TI AM64x Sita4ra is a new version of the K3 SoC family for industrial control, motor control, remote IO, IoT gateway etc., similar to the older AM65x family. Two reference machines are added alongside. Among the newly added machines, there is a very clear skew towards 64-bit machines now, with 12 32-bit machines compared to 23 64-bit machines. The full list sorted by SoC is: - ASpeed AST2500 BMC: ASRock E3C246D4I Xeon server board - Allwinner A10: Topwise A721 Tablet - Amlogic GXL: MeCool KII TV box - Amlogic GXM: Mecool KIII, Minix Neo U9-H TV boxes - Broadcom BCM4908: TP-Link Archer C2300 V1 router - MStar SSD202D: M5Stack UnitV2 camera - Marvell Armada 38x: ATL-x530 ethernet switch - Mediatek MT8183 Chromebooks: Lenovo 10e, Acer Spin 311, Asus Flip CM3, Asus Detachable CM3 - Mediatek MT8516/MT8183: OLogic Pumpkin Board - NXP i.MX7: reMarkable Tablet - NXP i.MX8M: Kontron pitx-imx8m, Engicam i.Core MX8M Mini - Nuvoton NPCM730: Quanta GBS BMC - Qualcomm X55: Telit FN980 TLB SoM, Thundercomm TurboX T55 SoM - Qualcomm MSM8998: OnePlus 5/5T phones - Qualcomm SM8350: Snapdragon 888 Mobile Hardware Development Kit - Rockchip RK3399: NanoPi R4S board - STM32MP1: Engicam MicroGEA STM32MP1 MicroDev 2.0 and SOM, EDIMM2.2 Starter Kit, Carrier, SOM - TI AM65: Siemens SIMATIC IOT2050 gateway There is notable work going into extending already supported machines and SoCs: - ASpeed AST2500 - Allwinner A23, A83t, A31, A64, H6 - Amlogic G12B - Broadcom BCM4908 - Marvell Armada 7K/8K/CN91xx - Mediatek MT6589, MT7622, MT8173, MT8183, MT8195 - NXP i.MX8Q, i.MX8MM, i.MX8MP - Qualcomm MSM8916, SC7180, SDM845, SDX55, SM8350 - Renesas R-Car M3, V3U - Rockchip RK3328, RK3399 - STEricsson U8500 - STMicroelectronics STM32MP141 - Samsung Exynos 4412 - TI K3-AM65, K3-J7200 - TI OMAP3 Among the treewide cleanups and bug fixes, two parts stand out: - There are a number of cleanups for issues pointed out by 'make dtbs_check' this time, and I expect more to come in the future as we increasingly check for regressions. - After a change to the MMC subsystem that can lead to unpredictable device numbers, several platforms add 'aliases' properties for these to give each MMC controller a fixed number" * tag 'arm-dt-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (516 commits) dt-bindings: mali-bifrost: add dma-coherent arm64: dts: amlogic: misc DT schema fixups arm64: dts: qcom: sc7180: Update iommu property for simultaneous playback arm64: dts: qcom: sc7180: pompom: Add "dmic_clk_en" + sound model arm64: dts: qcom: sc7180: coachz: Add "dmic_clk_en" ARM: dts: mstar: Add a dts for M5Stack UnitV2 dt-bindings: arm: mstar: Add compatible for M5Stack UnitV2 dt-bindings: vendor-prefixes: Add vendor prefix for M5Stack arm64: dts: mt8183: fix dtbs_check warning arm64: dts: mt8183-pumpkin: fix dtbs_check warning ARM: dts: aspeed: tiogapass: add hotplug controller ARM: dts: aspeed: amd-ethanolx: Enable all used I2C busses ARM: dts: aspeed: Rainier: Update to pass 2 hardware ARM: dts: aspeed: Rainier 1S4U: Fix fan nodes ARM: dts: aspeed: Rainier: Fix humidity sensor bus address ARM: dts: aspeed: Rainier: Fix PCA9552 on bus 8 ARM: dts: qcom: sdx55: add IPA information ARM: dts: qcom: sdx55: Add basic devicetree support for Thundercomm T55 dt-bindings: arm: qcom: Add binding for Thundercomm T55 kit ARM: dts: qcom: sdx55: Add basic devicetree support for Telit FN980 TLB ...
| * ARM: dts: stm32: Add PTP clock to Ethernet controllerKurt Kanzenbach2021-04-011-0/+2
| | | | | | | | | | | | | | | | | | | | Add the PTP clock to the Ethernet controller. Otherwise, the driver uses the main clock to derive the PTP frequency which is not necessarily the correct one. Tested with linuxptp on Olimex STMP1-OLinuXino-LIME2. Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * ARM: dts: stm32: enable the analog filter for all I2C nodes in stm32mp151Alain Volmat2021-03-291-0/+6
| | | | | | | | | | | | | | Enable the analog filter for all I2C nodes of the stm32mp151. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* | ARM: dts: stm32: Add wakeup management on stm32mp15x UART nodesErwan Le Ray2021-03-231-8/+16
|/ | | | | | | | | | | | | | | | | Add EXTI lines to the following UART nodes which are used for wakeup from CStop. - EXTI line 26 to USART1 - EXTI line 27 to USART2 - EXTI line 28 to USART3 - EXTI line 29 to USART6 - EXTI line 30 to UART4 - EXTI line 31 to UART5 - EXTI line 32 to UART7 - EXTI line 33 to UART8 Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Link: https://lore.kernel.org/r/20210319184253.5841-6-erwan.leray@foss.st.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: dts: stm32: add #clock-cells property to usbphyc node on stm32mp151Amelie Delaunay2021-01-291-0/+1
| | | | | | | | | usbphyc is a 48Mhz clock provider: the clock can be used as clock source for USB OTG. Add #clock-cells property to usbphyc node to reflect this capability. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on stm32mp151Amelie Delaunay2021-01-291-0/+2
| | | | | | | | | vdda1v1 and vdda1v8 supplies are required by USB PLL. Add them in usbphyc node. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: Rename mmc controller nodes to mmc@Marek Vasut2021-01-251-3/+3
| | | | | | | | | | | | | | Per mmc-controller.yaml, the node pattern is "^mmc(@.*)?$" , so adjust the node. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Ludovic Barre <ludovic.barre@st.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com Cc: devicetree@vger.kernel.org Acked-by: Yann Gautier <yann.gautier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* ARM: dts: stm32: support child mfd cells for the stm32mp1 TAMP sysconAhmad Fatoum2020-11-261-1/+1
| | | | | | | | | | | | | | | | The stm32mp1 TAMP peripheral has 32 backup registers that survive a warm reset. This makes them suitable for storing a reboot mode, which the vendor's kernel tree is already doing[0]. The actual syscon-reboot-mode child node can be added by a board.dts or fixed up by the bootloader. For the child node to be probed, the compatible needs to include simple-mfd. The binding now specifies this, so have the SoC dtsi adhere to it. [0]: https://github.com/STMicroelectronics/linux/commit/2e9bfc29dd Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: update stm32mp151 for remote proc synchronization supportArnaud Pouliquen2020-11-261-0/+7
| | | | | | | | | | | | | Two backup registers are used to store the Cortex-M4 state and the resource table address. Declare the tamp node and add associated properties in m4_rproc node to allow Linux to attach to a firmware loaded by the first boot stages. Associated driver implementation is available in commit 9276536f455b3 ("remoteproc: stm32: Parse syscon that will manage M4 synchronisation"). Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: adjust USB OTG gadget fifo sizes in stm32mp151Amelie Delaunay2020-11-261-2/+2
| | | | | | | | | Defaut use case on stm32mp151 USB OTG is ethernet gadget, using EP1 bulk endpoint (MPS=512 bytes) and EP2 interrupt endpoint (MPS=16 bytes). This patch optimizes USB OTG FIFO sizes accordingly. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: fix dmamux reg property on stm32mp151Amelie Delaunay2020-11-261-1/+1
| | | | | | | | | Reg property length should cover all DMAMUX_CxCR registers. DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest offset is at 0x3c, so length should be 0x40. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: fix mdma1 clients channel priority level on stm32mp151Amelie Delaunay2020-11-261-3/+3
| | | | | | | Update mdma1 clients channel priority level following stm32-mdma bindings. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: Add LP timer wakeup-source on stm32mp151Fabrice Gasnier2020-11-261-0/+5
| | | | | | | | LP timer can be used to wakeup from stop mode on stm32mp151. Add wakeup-source properties to all LP timer instances. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: Add LP timer irqs on stm32mp151Fabrice Gasnier2020-11-261-0/+5
| | | | | | | Add all LP timer irqs on stm32mp151. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: update sdmmc IP version for STM32MP15Yann Gautier2020-11-261-3/+3
| | | | | | | | | | | | | | Update the IP version to v2.0, which supports linked lists in internal DMA, and is present in STM32MP1 SoCs. The mmci driver supports the v2.0 periph id since 7a2a98be672b ("mmc: mmci: Add support for sdmmc variant revision 2.0"), so it's now Ok to add it into the SoC device tree to benefit from the improved DMA support. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: Harmonize EHCI/OHCI DT nodes name on stm32mp15Serge Semin2020-11-261-2/+2
| | | | | | | | | | | | | In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Amelie Delaunay <amelie.delaunay@st.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: fix DCMI DMA features on stm32mp15 familyHugues Fruchet2020-11-171-1/+1
| | | | | | | Enable FIFO mode with half-full threshold. Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: add arm-pmu node on stm32mp15Alexandre Torgue2020-09-231-0/+7
| | | | | | | | | Add arm-pmu node on stm32mp15. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Marek Vasut <marex@denx.de> # update to linux-next Tested-by: Marek Vasut <marex@denx.de> # on DH PDK2 and Avenger96 Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: add FMC2 EBI support for stm32mp157cChristophe Kerello2020-09-231-14/+29
| | | | | | | This patch adds FMC2 External Bus Interface support on stm32mp157c. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: Add compatibles for syscon for stm32mp151Benjamin Gaignard2020-07-211-1/+1
| | | | | | | Syscon nodes needs at least 2 compatibles to be compliant why yaml documentation. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: Add missing #address and #size cells on spi node for stm32mp151Benjamin Gaignard2020-06-151-0/+2
| | | | | | | Add the missing #address-cells and #size-cells to spi node. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: bump PSCI to version 1.0 on stm32mp15xEtienne Carriere2020-05-071-3/+1
| | | | | | | | Declare PSCI v1.0 support instead of v0.1 as the former is supported by the PSCI firmware stacks stm32mp15x relies on. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
* ARM: dts: stm32: add Fast Mode Plus info in I2C nodes of stm32mp151Alain Volmat2020-04-281-0/+6
| | | | | | | | Add the syscfg-fmp property in each i2c node in order to allow Fast Mode Plus speed if clock-frequency >= 1MHz is indicated. Signed-off-by: Alain Volmat <alain.volmat@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-23 06:01:20 +0100