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* ARM: tegra: Rename CPU and EMC OPP table device-tree nodesDmitry Osipenko2021-12-141-2/+2
| | | | | | | | | OPP table name now should start with "opp-table" and OPP entries shouldn't contain commas and @ signs in accordance to the new schema requirement. Reorganize CPU and EMC OPP table device-tree nodes. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Clean up external memory controller nodesThierry Reding2021-12-141-211/+221
| | | | | | | The external memory controller should be sorted after the memory controller to keep the ordering by unit-address intact. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Add EMC OPP and ICC properties to Tegra124 EMC and ACTMON ↵Dmitry Osipenko2020-11-261-0/+8
| | | | | | | | | | | | | | | device-tree nodes Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Update board device-trees by removing unsupported EMC OPPs. Note that ACTMON watches all memory interconnect paths, but we use a single CPU-READ interconnect path for driving memory bandwidth, for simplicity. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Rename EMC on Tegra124Thierry Reding2020-01-091-1/+1
| | | | | | | Rename the EMC node to external-memory-controller according to device tree best practices. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Convert to SPDX license tags for Tegra124 ApalisIgor Opaniuk2019-04-171-37/+2
| | | | | | | | | Replace boiler plate licenses texts with the SPDX license identifiers in Colibri/Apalis DTS files. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> [treding@nvidia.com: drop unneeded parentheses, keep license at X11] Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Initial support for Apalis TK1Marcel Ziswiler2016-07-111-0/+1502
This patch adds the device tree to support Toradex Apalis TK1 a computer on module which can be used on different carrier boards. The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec. Furthermore, there is a Kinetis MK20DN512 companion micro controller for analogue, CAN and resistive touch functionality which is not yet supported. Anything that is not self contained on the module is disabled by default. The device tree for the Evaluation Board includes the module's device tree and enables the supported peripherals of the carrier board (the Evaluation Board supports almost all of them). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>