| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller
and NAND chips"), the Denali NAND controller driver migrated to the
new controller/chip representation.
Update DT for it.
In the new binding, the number of connected chips are described in
DT instead of run-time probed.
I added just one chip to the reference boards, where we do not know
if the on-board NAND device is a single chip or multiple chips.
If we added too many chips into DT, it would end up with the timeout
error in nand_scan_ident().
I changed all the pinctrl properties to use the single CS.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
| |
Add SD controller nodes for LD4, Pro4, sLD8, Pro5, and PXs2.
This is also used as an eMMC controller for LD4, Pro4, and sLD8.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
| |
Add nodes of SPI controller for LD4, Pro4, sLD8, Pro5 and PXs2.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
|
|
| |
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
According to Documentation/process/license-rules.rst, move the SPDX
License Identifier to the very top of the file. I used C++ comment
style not only for the SPDX line but for the entire block because
this seems Linus' preference [1]. I also dropped the parentheses to
follow the examples in that document.
[1] https://lkml.org/lkml/2017/11/25/133
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
| |
Add efuse node for UniPhier LD4, Pro4, sLD8, Pro5 and PXs2.
This efuse node is included in soc-glue.
Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
| |
Add resets properties to all nodes that have reset lines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
| |
The GPIO controller also acts as an interrupt controller and the
interrupt lines are connected to the AIDET block.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fix warnings like follows:
Warning (node_name_chars_strict): Character '_' not recommended in ...
Commit 8654cb8d0371 ("dtc: update warning settings for new bus and
node/property name checks") says these checks are a bit subjective,
but Rob also says to not add new W=2 warnings.
The exising warnings should be fixed in order to catch new ones
easily.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
| |
All registers are located within 0x400 size from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
| |
Add UniPhier AIDET (ARM Interrupt Detector) nodes to support
active low interrupts.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
|
| |
Add NAND controller node to LD4, Pro4, sLD8, Pro5, and PXs2.
Set up pinctrl to enable 2 chip select lines except Pro4. The CS1
for Pro4 is multiplexed with other peripherals such as UART2, so
I did not enable it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
| |
To include dt-bindings headers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
| |
Commit fa53757bca33 ("ARM: dts: uniphier: use SPDX-License-Identifier")
missed to touch these two. Now updating.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
|
|
| |
Compiling the UniPhier DT files with W=1, DTC warns like follows:
Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/ethernet@00000000 simple-bus unit address format error, expected "0"
Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/uart@000b0000 simple-bus unit address format error, expected "b0000"
Warning (simple_bus_reg): Node /soc/smpctrl@59800000 simple-bus unit address format error, expected "59801000"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
| |
Commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as
deprecated") declared that skeleton.dtsi was deprecated.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
I notice some mistakes in the SoC DTSI; wrong interrupts properties
of timer nodes, mismatch between the node name and the compatible
for sdctrl block. Given those problems fixed, the common parts
among SoCs are less than I had first expected. The more and more
property overrides are making the SoC DTSI unreadable.
Stretch out the SoC DTSI files and fix the following:
- Fix the 3rd cell of the interrupts property of the timer nodes
for Pro4, Pro5, PXs2
- Fix the node name mioctrl to sdctrl for Pro5, PXs2
- Fix the second region of l2 node for PXs2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
| |
Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
|
| |
|
|
|
|
|
| |
I made a mistake bacuse the Media I/O block is not implemented in
these SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
|
|
| |
The UniPhier reset controller driver has been merged. Enable it.
Also, replace the fixed-rate clocks with the dedicated clock
drivers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| |
|
|
|
|
| |
Use PSCI for enable-method instead of SoC specific implementation.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
|
All UniPhier device trees have the common prefix "uniphier-", so
"ph1-" is just making names longer. Recent documents and other
projects are not using PH1- prefixes any more.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
