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* ARM: l2x0: Add explicit includes for init and typesRob Herring2023-08-121-0/+2
| | | | | | | | | The cache-l2x0.h header uses u32 type and the __init and __iomem attributes, so it should have explicit includes for those. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230803-dt-header-cleanups-for-soc-v2-1-d8de2cc88bff@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: l2c: add definition for FWA in PL310 aux registerLubomir Rintel2019-10-171-0/+2
| | | | | | | The PL310 also has a "Force write allocate" bits in the Auxiliary Control Register. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333Thomas Gleixner2019-06-051-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 136 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.384967451@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 8611/1: l2x0: add PMU supportMark Rutland2016-09-061-0/+19
| | | | | | | | | | | | | | | | | | | | | | The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary. This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Tested-by: Kim Phillips <kim.phillips@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: trial at enabling some Cortex-A9 optimisationsRussell King2014-05-301-0/+8
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of thisRussell King2014-05-301-1/+0
| | | | | | | | L2X0_AUX_CTRL_MASK is not useful for PL310s. It would be better if people thought about their value for this rather than cargo-cult programming. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: fix register namingRussell King2014-05-301-25/+48
| | | | | | | | | | | | | We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add and use L2C revision constantsRussell King2014-05-301-6/+16
| | | | | | | The revision namespace is specific to the L2 cache part, so don't name these with generic identifiers, use a part specific identifier. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7922/1: l2x0: add Marvell Tauros3 supportSebastian Hesselbarth2013-12-291-0/+1
| | | | | | | | | | | | | This adds support for the Marvell Tauros3 cache controller which is compatible with pl310 cache controller but broadcasts L1 cache operations to L2 cache. While updating the binding documentation, clean up the list of possible compatibles. Also reorder driver compatibles to allow non-ARM derivated to be compatible to ARM cache controller compatibles. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrlGregory CLEMENT2012-11-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as: - no cache id part number available through hardware (need to get it by the DT). - always write through mode available. - two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation). - in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line. Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7546/1: cache-l2x0: add an optional register to save/restoreGregory CLEMENT2012-10-181-0/+1
| | | | | | | | Tested-and-Reviewed-by: Yehuda Yitschak <yehuday@marvell.com> Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: cache-l2x0.c: consistently use u32Russell King2012-01-201-3/+3
| | | | | | | | | | __u32 exists to avoid namespace clashes with userspace programs. It should not be used outside header files, so convert to use u32 instead. Also, don't mix uint32_t and __u32 - use the same type throughout the file for consistency. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7156/1: l2x0: fix compile error on !CONFIG_USE_OFOlof Johansson2011-11-121-0/+2
| | | | | | | | | | | | | | | | | | | fae2b89ab1 (ARM: l2x0: add empty l2x0_of_init) adds a static inline function that returns -ENODEV, but at least on tegra cache-l2x0.h is included without errno.h being pulled in first, resulting in compile errors if OF isn't enabled: In file included from arch/arm/mach-tegra/common.c:26: arch/arm/include/asm/hardware/cache-l2x0.h: In function 'l2x0_of_init': arch/arm/include/asm/hardware/cache-l2x0.h:110: error: 'ENODEV' undeclared (first use in this function) arch/arm/include/asm/hardware/cache-l2x0.h:110: error: (Each undeclared identifier is reported only once arch/arm/include/asm/hardware/cache-l2x0.h:110: error: for each function it appears in.) Add errno.h to the include file to make it self-contained. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2x0: add empty l2x0_of_initRob Herring2011-10-311-1/+8
| | | | | | | | Add empty version of l2x0_of_init for when CONFIG_CACHE_L2X0 is not selected. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Barry Song <21cnbao@gmail.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure modeBarry Song2011-10-171-0/+25
| | | | | | | | | | | we save the l2x0 registers at the first initialization, and platform codes can get them to restore l2x0 status after wakeup. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7009/1: l2x0: Add OF based initializationRob Herring2011-10-171-0/+17
| | | | | | | | | | | | | This adds probing for ARM L2x0 cache controllers via device tree. Support includes the L210, L220, and PL310 controllers. The binding allows setting up cache RAM latencies and filter addresses (PL310 only). Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7080/1: l2x0: make sure I&D are not locked down on initLinus Walleij2011-09-071-2/+7
| | | | | | | | | | | | | | | | | | | Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state. Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Adrian Bunk <adrian.bunk@movial.com> Cc: Rob Herring <robherring2@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Jan Rinze <janrinze@gmail.com> Tested-by: Robert Marklund <robert.marklund@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.Srinivas Kandagatla2011-08-151-1/+1
| | | | | | | | | | | | | | | | | | | This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits. The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations. It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small) and also prints incorrect cachesize. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: stable@kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6741/1: errata: pl310 cache sync operation may be faultySrinidhi Kasagar2011-02-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | The effect of cache sync operation is to drain the store buffer and wait for all internal buffers to be empty. In normal conditions, store buffer is able to merge the normal memory writes within its 32-byte data buffers. Due to this erratum present in r3p0, the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. This can severely affect performance on the write traffic esp. on Normal memory NC one. The proposed workaround is to replace the normal offset of cache sync operation(0x730) by another offset targeting an unmapped PL310 register 0x740. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2x0: Add aux control register bitfieldsSantosh Shilimkar2010-12-181-1/+11
| | | | | | | | | | This patch adds the PL310 Auxiliary Control Register bitfields so that SOC's can use these bit fields to construct the AUXCTRL value to be passed/programmed instead of hardcoding it. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'l2x0-pull-rmk' of ↵Russell King2010-10-281-3/+6
|\ | | | | | | git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into devel-stable
| * ARM: l2x0: Determine the cache sizeSantosh Shilimkar2010-10-261-0/+1
| | | | | | | | | | | | | | | | | | The cache size is needed for to optimise range based maintainance operations Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
| * ARM: l2x0: Fix coding-style in the cache-l2x0.hSantosh Shilimkar2010-10-261-3/+5
| | | | | | | | | | | | | | | | | | Replace tab with space after #define to be consisten with other define in the file. Also move the bit mask below the register offsets. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
* | ARM: Add L2X0 PREFETCH and POWER control registerKyungmin Park2010-10-251-0/+4
|/ | | | | | | | This patch adds L2X0 Prefetch and Power control register. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310Jason McMullan2010-05-151-0/+3
| | | | | | | | | | | | | | | | The L310 cache controller's interface is almost identical to the L210. One major difference is that the PL310 can have up to 16 ways. This change uses the cache's part ID and the Associativity bits in the AUX_CTRL register to determine the number of ways. Also, this version prints out the CACHE_ID and AUX_CTRL registers. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* RealView: Add support for the RealView/PBX platformColin Tuckley2009-05-301-0/+2
| | | | | | | | | This is a RealView platform supporting core tiles with ARM11MPCore, Cortex-A8 or Cortex-A9 (multicore) processors. It has support for MMC, CompactFlash, PCI-E. Signed-off-by: Colin Tuckley <colin.tuckley@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* [ARM] move include/asm-arm to arch/arm/include/asmRussell King2008-08-021-0/+56
Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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