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* Merge branch 'devel-stable' into develRussell King2011-01-066-4/+101
|\ | | | | | | | | | | Conflicts: arch/arm/mach-pxa/clock.c arch/arm/mach-pxa/clock.h
| * Merge branch 'master' of git://git.infradead.org/users/cbou/linux-cns3xxx ↵Russell King2011-01-036-4/+101
| |\ | | | | | | | | | into devel-stable
| | * ARM: cns3xxx: Add architecture definition for EHCI/OHCI controllerMac Lin2010-11-264-2/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add plateform_device for EHCI and OHCI controller on CNS3XXX. Power reference count (usb_pwr_ref) is used to control enabling and disabling the single clock control for both EHCI and OHCI controller. It also removes EHCI/OHCI unused virtual address definitions. Signed-off-by: Mac Lin <mkl0301@gmail.com> Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
| | * ARM: cns3xxx: Add new and export the old power management functionsMac Lin2010-11-264-2/+38
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds cns3xxx_pwr_clk_dis, and exports these power management functions that may be used by many other device drivers on CNS3XXX. Signed-off-by: Mac Lin <mkl0301@gmail.com> Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
| | * ARM: cns3xxx: Make cns3xxx_pwr_soft_rst_force() to actually reset blocksAnton Vorontsov2010-11-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6eb5d146d4535 ("ARM: cns3xxx: Use IO memory accessors everywhere") breaks cns3xxx_pwr_soft_rst_force() function, so that it doesn't write cleared bit into the register. This patch fixes the issue by adding the necessary __raw_writel(). Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
* | | Merge branch 'misc' into develRussell King2011-01-061-0/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/common/Makefile arch/arm/kernel/Makefile arch/arm/kernel/smp.c
| * | | ARM: 6520/1: Kconfig: add new symbol MIGHT_HAVE_PCIHans Ulli Kroll2010-12-051-0/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Today more boards with arm cpu have selectable pci bus. This patch makes this more scalable and remove line continuations in Kconfig Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: GIC: private a standard get_irqnr_preamble assembler macroRussell King2010-12-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a standard get_irqnr_preamble assembler macro for platforms to use, which retrieves the base address of the GIC CPU interface from gic_cpu_base_addr. Allow platforms to override this by defining HAVE_GET_IRQNR_PREAMBLE. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: GIC: consolidate gic_cpu_base_addr to common GIC codeRussell King2010-12-142-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: GIC: provide a single initialization function for boot CPURussell King2010-12-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: 6476/1: Use shared GIC entry macros on CNS3XXXMagnus Damm2010-12-071-60/+1
| |/ |/| | | | | | | | | | | | | Use the GIC demux code in asm/hardware/entry-macro-gic.S on the CNS3XXX subarchitecture. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: cns3xxx: Fix build with CONFIG_PCI=yAnton Vorontsov2010-11-291-1/+1
|/ | | | | | | | | | | | | | | commit 6338a6aa7c082f11d55712251e14178c68bf5869 ("ARM: 6269/1: Add 'code' parameter for hook_fault_code()") breaks CNS3xxx build: CC arch/arm/mach-cns3xxx/pcie.o pcie.c: In function 'cns3xxx_pcie_init': pcie.c:373: warning: passing argument 4 of 'hook_fault_code' makes integer from pointer without a cast pcie.c:373: error: too few arguments to function 'hook_fault_code' This commit fixes the small issue. Cc: stable@kernel.org [36] Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
* arm: remove machine_desc.io_pg_offst and .phys_ioNicolas Pitre2010-10-201-2/+0
| | | | | | | | | | | | | | | Since we're now using addruart to establish the debug mapping, we can remove the io_pg_offst and phys_io members of struct machine_desc. The various declarations were removed using the following script: grep -rl MACHINE_START arch/arm | xargs \ sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }' [ Initial patch was from Jeremy Kerr, example script from Russell King ] Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Eric Miao <eric.miao at canonical.com>
* arm: return both physical and virtual addresses from addruartJeremy Kerr2010-10-201-6/+4
| | | | | | | | | | | | | | | | | | | | Rather than checking the MMU status in every instance of addruart, do it once in kernel/debug.S, and change the existing addruart macros to return both physical and virtual addresses. The main debug code can then select the appropriate address to use. This will also allow us to retreive the address of a uart for the MMU state that we're not current in. Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com> and Tony Lindgren <tony@atomide.com>, and fix for versatile express from Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>. Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
* ARM: cns3xxx: Add support for AHCI controllersAnton Vorontsov2010-06-083-0/+54
| | | | | | | CNS3xxx chips have AHCI-compatible SATA controller. This patch adds the support using generic ahci_platform driver. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
* ARM: cns3xxx: Add support for SDHCI controllersAnton Vorontsov2010-06-084-1/+82
| | | | | | | CNS3xxx chips have SDHCI-compatible SDIO/SD/MMC controller. This patch adds the support using sdhci-cns3xxx driver. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
* ARM: cns3xxx: Add support for PCI Express portsAnton Vorontsov2010-06-082-0/+390
| | | | | | | | | This patch adds PCIe support for CNS3xxx-based boards. The support was tested with a directly attached SKY2 NIC, and EHCI USB controller behind the PLX PEX8112 P2P bridge (to make sure that type1 cfg cycles work as expected). Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
* ARM: cns3xxx: Use IO memory accessors everywhereAnton Vorontsov2010-06-082-54/+68
| | | | | | | | | | Before it isn't too late let's switch to IO memory accessors. This patch converts all current _REG users and _REG definitions. There should be no functional changes. Suggested-by: Ben Dooks <ben-linux@fluff.org> Suggested-by: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
* ARM: cns3xxx: Add CNS3420 Validation Board supportAnton Vorontsov2010-05-023-0/+157
| | | | | | | | This patch adds support for CNS3420VB rev 1.3 boards. With this patch CNS3420VB boards are able to boot up to the userspace, with a console available on UART0. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
* ARM: cns3xxx: Add basic support for Cavium Networks CNS3xxx processorsAnton Vorontsov2010-05-0217-0/+1300
This patch adds very basic support for ECONA CNS3xxx ARM11 MPcore (ARMv6) dual-core processors. Note that SMP is not yet supported, as well as many peripheral devices. Support for these features will be added later. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
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