summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-davinci/cdce949.c (follow)
Commit message (Collapse)AuthorAgeFilesLines
* ARM: drivers: remove __dev* attributes.Greg Kroah-Hartman2013-01-041-2/+2
| | | | | | | | | | | | | | | CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm: fix implicit module.h users by adding it to arch/arm as required.Paul Gortmaker2011-11-011-0/+1
| | | | | | | These files will fail to compile if we dont clean them up in advance and have them include the appropriate headers they need. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* davinci: misc cleanups from sparseKevin Hilman2010-05-071-0/+1
| | | | | | | | - Convert data/functions to static - include headers for missing declarations - pointer cleanups: struct foo *__iomem f --> struct foo __iomem *f; Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: clock: let clk->set_rate function sleepSekhar Nori2010-02-041-3/+7
| | | | | | | | | | | | | | | When supporting I2C/SPI based on-board PLLs like CDCE949, it is essential that clk->set_rate be able to sleep. Currently, this is not possible because clk->set_rate is called from within spin-lock in clk_set_rate This patch brings clk->set_rate outside of the spin-lock and lets the individual set_rate implementations achieve serialization through appropiate means. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: add support for CDCE949 clock synthesizerNageswari Srinivasan2010-02-041-0/+289
This patch adds support for TI's CDCE949 - a clock synthesizer with 4 PLLs and 9 outputs. It is used on DM6467 EVM. On the EVM, it generates clocks required for VPIF, TSIF and Audio modules. This patch adds it as part of the DaVinci clock framework. Testing: The various frequency outputs on Y1 have been tested using a out-of-tree VPIF video driver supporting HD video. The register values for Y5 frequency outputs have been derived from TSIF driver sources in MontaVista LSP kernel, but actual output has not been tested for lack of TSIF driver which actually works on the latest kernel. Signed-off-by: Nageswari Srinivasan <nageswari@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>