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* ARM: imx6q: remove board specific CLKO setupShawn Guo2013-08-221-0/+11
| | | | | | | | | | | The CLKO is widely used by imx6q board designs to clock audio codec. Since most codecs accept 24 MHz frequency, let's initially set up CLKO with OSC24M (cko <-- cko2 <-- osc). Then those board specific CLKO setup for audio codec can be removed. The board dts files also need an update on cko reference in codec node. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add vdoa gate clockShawn Guo2013-08-221-1/+2
| | | | | | Add the missing vdoa gate clock for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add the missing cko output selectionShawn Guo2013-08-221-1/+3
| | | | | | | | The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and there is a multiplexer to select between cko1 and cko2. Add this missing selection as the clock cko. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add cko2 clocksShawn Guo2013-08-221-1/+14
| | | | | | | It adds the missing cko2 clocks, including multiplexer, divider and gate. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: add spdif gate clockShawn Guo2013-08-221-1/+3
| | | | | | It adds the missing spdif gate clock into imx6q clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: change some clocks to fixup clocksLiu Ying2013-08-161-12/+12
| | | | | | | | | | All the clocks controlled by the register 'CCM Serial Clock Multiplexer Register 1' should be fixup clocks. This patch changes those clocks from basic multiplexer or divider clocks to fixup clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DLPhilipp Zabel2013-08-161-1/+1
| | | | | | | i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6Q: correct emi_sel clock muxingLiu Ying2013-07-151-2/+3
| | | | | | | | | | | | | | The correct muxing for emi_sel clock should be 2b'00 - 396M PFD 2b'01 - PLL3 2b'10 - AXI clk root 2b'11 - 352M PFD This patch corrects the muxing in the clock driver. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresdNicolin Chen2013-06-171-0/+2
| | | | | | | WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: use common of_clk_init() call to initialize clocksShawn Guo2013-06-171-6/+3
| | | | | | | | Instead of explicitly calling clock initialization functions, we can declare the functions with CLK_OF_DECLARE() and then call common of_clk_init() to have them invoked properly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: call of_clk_init() to register fixed rate clocksShawn Guo2013-06-171-14/+5
| | | | | | | As the fixed rate clocks are defined in device tree, we can just call of_clk_init() to register them. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6: clk: add different DualLite MLB clock configDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock configuration. Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: clk: add the eim_slow clockHuang Shijie2013-06-171-1/+2
| | | | | | | Add the eim_slow clock, since the weim needs it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: disable pll8_mlb in mx6q_clksJiada Wang2013-06-171-1/+0
| | | | | | | | | | | The MLB PLL clock's operation doesn't fit for clock framework and it should be handled internally in MLB driver. Remove initialization of pll8_mlb clock device but leave its declaration in mx6q_clks to avoid affecting imx6q clock numbering. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6: clk: add i.MX6 DualLite differencesDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and moves the gpu2_core configuration at that place. Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences by using cpu_is_mx6dl(). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: clk-imx6q: AXI clock select index is incorrectAnson Huang2013-06-031-1/+1
| | | | | | | | | | | | The AXI clock mux should be as below: 00: periph; 01: pll2_pfd2_396m; 10: periph; 11: pll3_pfd1_540m; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: fix for ldb_di_selsJiada Wang2013-05-231-1/+1
| | | | | | | | | | As pll5_video_div has been introduced to represent the clock generated from post-divider for video. Instead of pll5_video, pll5_video_div should be proper root clock for ldb_di_sel. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: fix typo in gpu3d_shader_selsShawn Guo2013-05-121-1/+1
| | | | | | | | There is no clock pll2_pfd9_720m. Instead it should be pll3_pfd0_720m. Fix the typo in gpu3d_shader_sels. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* ARM i.MX6: correct MLB clock configurationDirk Behme2013-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | According to the i.MX6 Dual/Quad technical reference manual (Figure 18-2. Clock Tree - Part 1) the MLB clock is directly feed by the AXI_CLK_ROOT. This is called 'axi' in our code. Note that the clock of the MLB IP block on the i.MX6 is completely independent of the PLL8 (MLB PLL). The MLB PLL isn't responsible for feeding the MLB IP block with a clock. Instead, it's used internally by the MLB module to sync the bus clock in case the MLB 6-pin interface is enabled: MediaLB Control 0 Register, MLB150_MLBC0[5], MLBPEN: 1 MediaLB 6-pin interface enabled. MLB PLL and MLB PHY is enabled in this case. I.e. the PLL8 MLB PLL has to be handled by the MLB driver and isn't needed for clocking the MLB module itself. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jiada Wang <Jiada_Wang@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocksPhilipp Zabel2013-05-121-3/+4
| | | | | | | | The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/ pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: add initial imx6dl supportShawn Guo2013-04-121-1/+1
| | | | | | | | The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly compatible with i.MX6 Quad/Dual. And that's why we choose to support it using imx6q code with cpu_is_imx6dl() check when necessary. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: set the LDB serial clock parent to the video PLLPhilipp Zabel2013-04-121-0/+5
| | | | | | | | | On i.MX6q revision 1.1 and later, set the video PLL as parent for the LDB clock branch. On revision 1.0, the video PLL is useless due to missing dividers, so keep the default parent (mmdc_ch1_axi). Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1Philipp Zabel2013-04-121-6/+34
| | | | | | | | Query silicon revision to determine clock tree and add post dividers for newer revisions. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: fix ldb di divider and selector clocksPhilipp Zabel2013-04-121-4/+4
| | | | | | | | Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate flags for the LDB display interface divider and selector clocks. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: enable RBC to support anatop LPM modeAnson Huang2013-04-121-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | RBC is to control whether some ANATOP sub modules can enter lpm mode when SOC is into STOP mode, if RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP will have below behaviors: 1. Digital LDOs(CORE, SOC and PU) are bypassed; 2. Analog LDOs(1P1, 2P5, 3P0) are disabled; As the 2P5 is necessary for DRAM IO pre-drive in STOP mode, so we need to enable weak 2P5 in STOP mode when 2P5 LDO is disabled. For RBC settings, there are some rules as below due to hardware design: 1. All interrupts must be masked during operating RBC registers; 2. At least 2 CKIL(32K) cycles is needed after the RBC setting is changed. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: enable periphery well bias for suspendAnson Huang2013-04-121-1/+29
| | | | | | | | Enable periphery charge pump for well biasing at suspend to reduce periphery leakage. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6: Fix ldb_di clock selectionDirk Behme2013-04-091-1/+1
| | | | | | | | | | According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b) of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root clock is named 'pll3_usb_otg', select this instead of the 540M clock. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: provide twd clock lookup from device treeShawn Guo2013-04-091-1/+0
| | | | | | | | | | | | | | | | | | While booting from device tree, imx6q used to provide twd clock lookup by calling clk_register_clkdev() in clock driver. However, the commit bd60345 (ARM: use device tree to get smp_twd clock) forces DT boot to look up the clock from device tree. It causes the failure below when twd driver tries to get the clock, and hence kernel has to calibrate the local timer frequency. smp_twd: clock not found -2 ... Calibrating local timer... 396.13MHz. Fix the regression by providing twd clock lookup from device tree, and remove the unused twd clk_register_clkdev() call from clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: pll1_sys should be an initial on clkShawn Guo2013-03-111-1/+1
| | | | | | | | | | We always boot from PLL1, so let's have pll1_sys in the clks_init_on list to have clk prepare/enable use count match the hardware status, so that drivers managing pll1_sys like cpufreq can get the use count right from the start. Reported-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge branch 'imx/cpuidle' into late/dtArnd Bergmann2013-02-191-1/+11
|\ | | | | | | | | | | | | | | | | | | This resolves one non-obvious merge conflict between the imx cpuidle patches and the imx DT changes for 3.9. Conflicts: arch/arm/mach-imx/mach-imx6q.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: imx6q: support WAIT mode using cpuidleShawn Guo2013-01-301-0/+12
| | | | | | | | | | | | | | | | Add WAIT mode (ARM core clock gating) support to imx6q cpuidle driver. As WAIT mode is broken on imx6q TO 1.0 and 1.1, it only enables the support for revision 1.2 with chicken bit set. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: remove unused imx6q_clock_map_io()Shawn Guo2013-01-291-2/+0
| | | | | | | | | | | | | | imx6q_clock_map_io() becomes an empty function since imx6q clock driver is moved to common clock framework. It's used nowhere now. Remove it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM i.MX6: change mxs usbphy clock usagePeter Chen2013-02-101-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This mxs usbphy is only needs to be on after system boots up, and software never needs to control it anymore. Meanwhile, usbphy's parent needs to be notified if usb is suspend or not. So we design below mxs usbphy usage: - usbphy1_gate and usbphy2_gate: Their parents are dummy clock, we only needs to enable it after system boots up. - usbphy1 and usbphy2 Usage reserved bit for this clock, in that case, the refcount will be updated, but without hardware changing. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: imx: correct low-power mode settingShawn Guo2013-01-141-0/+3
|/ | | | | | | | | | | The hardware reset value of bit CCM_CLPCR_LPM enables WAIT mode (WAIT_UNCLOCKED) by default. However this is undesirable because WAIT mode should only be enabled when there is a driver managing ARM clock gating. Correct the initial power mode to WAIT_CLOCKED (disable WAIT mode). While at it, the power mode after resuming is also set back to WAIT_CLOCKED from STOP_POWER_OFF. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-12-131-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC device tree conversions and enablement from Olof Johansson: "Continued device tree conversion and enablement across a number of platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other smaller series as well. ux500 has seen continued conversion for platforms. Several platforms have seen pinctrl-via-devicetree conversions for simpler multiplatform. Tegra is adding data for new devices/drivers, and Exynos has a bunch of new bindings and devices added as well. So, pretty much the same progression in the right direction as the last few releases." Fix up conflicts as per Olof. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (185 commits) ARM: ux500: Rename dbx500 cpufreq code to be more generic ARM: dts: add missing ux500 device trees ARM: ux500: Stop registering the PCM driver from platform code ARM: ux500: Move board specific GPIO info out to subordinate DTS files ARM: ux500: Disable the MMCI gpio-regulator by default ARM: Kirkwood: remove kirkwood_ehci_init() from new boards ARM: Kirkwood: Add support LED of OpenBlocks A6 ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6 ARM: kirkwood: Add NAND partiton map for OpenBlocks A6 ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6 ARM: kirkwood: Add support DT of second I2C bus ARM: kirkwood: Convert mplcec4 board to pinctrl ARM: Kirkwood: Convert km_kirkwood to pinctrl ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl ARM: Kirkwood: Convert IX2-200 to pinctrl. ARM: Kirkwood: Convert lsxl boards to pinctrl. ARM: Kirkwood: Convert ib62x0 to pinctrl. ARM: Kirkwood: Convert GoFlex Net to pinctrl. ARM: Kirkwood: Convert dreamplug to pinctrl. ARM: Kirkwood: Convert dockstar to pinctrl. ...
| * ARM: imx: enable cpufreq for imx6qShawn Guo2012-11-161-0/+1
| | | | | | | | | | | | It enables cpufreq support for imx6q with generic cpufreq-cpu0 driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM i.MX6: remove gate_mask from pllv3Sascha Hauer2012-11-221-9/+9
| | | | | | | | | | | | | | | | | | | | Now that the additional enable bits in the enet PLL are handled as gates, the gate_mask is identical for all plls. Remove the gate_mask from the code and use the BM_PLL_ENABLE bit for enabling/disabling the PLL. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM i.MX6: Fix ethernet PLL clocksSascha Hauer2012-11-221-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz and has different outputs. Only the enet reference clock is implemented. This patch changes the PLL so that it outputs 500MHz and adds the additional outputs as dividers. This now matches the datasheet which says: > This PLL synthesizes a low jitter clock from 24 MHz reference clock. > The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are: > • Ref_PCIe = 125 MHz > • Ref_SATA = 100 MHz > • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM i.MX6: rename PLLs according to datasheetSascha Hauer2012-11-221-4/+4
| | | | | | | | | | | | | | | | | | In recent reference manuals the PLLs were renumbered. PLL8 now is PLL6 and vice versa. Change the code according to the reference manual to avoid confusion. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM i.MX6: fix ldb_di_sel muxSteffen Trumtrar2012-11-161-1/+1
|/ | | | | | | | This adds the mmdc_ch1 as a possible parent for the ldb_di clk. According to the datasheet, this clock can be selected at this mux. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: include common.h rather than mach/common.hShawn Guo2012-10-151-1/+2
| | | | | | | | | | | | Rename mach-imx/include/mach/common.h to mach-imx/common.h and update all users to include common.h rather than mach/common.h. It also removes an unneeded inclusion to common.h in mach-imx/devices/devices.c. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'imx-dt-3.7-2' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Olof Johansson2012-09-211-0/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | into next/dt From Shawn Guo: This is the second round of imx-dt patches for 3.7. It's based on and imx-dt-3.7 and imx-clk-dt-lookup which have already been pulled. * tag 'imx-dt-3.7-2' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent ARM: dts: imx6q-sabrelite: add usbotg pinctrl support ARM: dts: imx6q-sabrelite: add usbmisc device
| * ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parentHuang Shijie2012-09-191-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | The gpmi-nand driver can support the ONFI nand chip's EDO (extra data out) mode in the asynchrounous mode. In the asynchrounous mode 5, the gpmi needs 100MHz clock for the IO. But with the pll2_pfd0_352m, we can not get the 100MHz clock. So choose pll2_pfd2_396m as enfc_sel's parent. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge tag 'imx-clk-dt-lookup' of ↵Olof Johansson2012-09-131-39/+5
|\| | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt It replaces the clk_register_clkdev in imx6q clock driver with DT lookup. It depends on Mike's clk-3.7 branch. * tag 'imx-clk-dt-lookup' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: imx6q: replace clk_register_clkdev with clock DT lookup Resolved context add/remove conflict in arch/arm/boot/dts/imx6q.dtsi
| * ARM: imx6q: replace clk_register_clkdev with clock DT lookupShawn Guo2012-09-111-39/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | It really becomes an maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx6q client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM i.MX6q: Add virtual 1/3.5 dividers in the LDB clock pathPhilipp Zabel2012-08-171-3/+5
|/ | | | | | | | | | | | | | | The ldb_di[01]_podf is implemented as a clk-divider that divides by 1 or 2. In reality, the ldb_di[01]_ipu_div dividers divide by either 3.5 or 7. Adding a fixed factor of 1/3.5 fixes their children's clock rates. This should probably be converted to rate table based dividers, once available. Cc: <stable@vger.kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-07-241-3/+19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull arm-soc device tree description updates from Arnd Bergmann: "This branch contains two kinds of updates: Some platforms in the process of getting converted to device tree based booting, and the platform specific patches necessary for that are included here. Other platforms are already converted, so we just need to update the actual device tree source files and the binding documents to add support for new board and new drivers. In the future we will probably separate those into two branches, and in the long run, the plan is to move the device tree source files out of the kernel repository, but that has to wait until we have completed a much larger portion of the binding documents." Fix up trivial conflicts in arch/arm/mach-imx/clk-imx6q.c due to newly added clkdev registers next to a few removed unnecessary ones. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits) ARM: LPC32xx: Add PWM to base dts file ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5 ARM: EXYNOS: Add spi clock support for EXYNOS5 ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4 ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock ARM: ux500: Remove PMU platform registration when booting with DT ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure ARM: ux500: Ensure vendor specific properties have the vendor's identifier pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree ARM: ux500: Apply ab8500-debug node do the db8500 DT structure ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT ...
| * ARM: imx6q: add usbphy clocksRichard Zhao2012-07-121-1/+6
| | | | | | | | | | Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6q: add usb controller clock lookupsRichard Zhao2012-07-121-0/+4
| | | | | | | | | | Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6q: add clocks for gpmi-nandHuang Shijie2012-07-031-1/+7
| | | | | | | | | | | | | | Add clocks for gpmi-nand. Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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