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* ARM: imx: select syscon for IMX6SLArnd Bergmann2013-06-241-0/+1
| | | | | | | | | This is required for building a kernel that enables only IMX6SL but not IMX6Q, which would get a build error when syscon is not available. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1Arnd Bergmann2013-06-241-0/+1
| | | | | | | | | This is required for building a kernel that enables only scb9328 and would not get the i.MX1 specific files otherwise. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Sascha Hauer <kernel@pengutronix.de>
* ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresdNicolin Chen2013-06-172-0/+44
| | | | | | | WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: Remove mxc specific ulpi access opsMarkus Pargmann2013-06-175-141/+22
| | | | | | | | | | | | | There are ulpi access ops implemented in drivers/usb/phy/phy-ulpi.c. mxc access ops implement the same access operations within mach-imx. This patch removes the mxc ulpi file and uses phy-ulpi instead for imx_otg_ulpi_create. phy-ulpi successfully tested with i.MX27 Phytec phyCARD-S (pca100). Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: add initial support for VF610Jingchang Lu2013-06-173-0/+65
| | | | | | | Add initial support for Freescale Vybrid VF610 SoC. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: add VF610 clock supportJingchang Lu2013-06-171-0/+319
| | | | | | | | | Add clock support for Vybrid VF610. It uses dtc macro support to define all clock IDs in vf610-clock.h to keep clock IDs coherence between kernel and DT. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: clk: No need to initialize phandle structFabio Estevam2013-06-171-1/+1
| | | | | | | | | | | | | commit 84344b43c (ARM: i.MX5: Allow DT clock providers) introduce the following sparse warning: arch/arm/mach-imx/clk.c:12:43: warning: Using plain integer as NULL pointer There is no need to initialize phandle, so remove it. Cc: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: irq-common: Include header to avoid sparse warningFabio Estevam2013-06-171-0/+1
| | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/irq-common.c:24:5: warning: symbol 'mxc_set_irq_fiq' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: use common of_clk_init() call to initialize clocksShawn Guo2013-06-175-16/+10
| | | | | | | | Instead of explicitly calling clock initialization functions, we can declare the functions with CLK_OF_DECLARE() and then call common of_clk_init() to have them invoked properly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: call of_clk_init() to register fixed rate clocksShawn Guo2013-06-171-14/+5
| | | | | | | As the fixed rate clocks are defined in device tree, we can just call of_clk_init() to register them. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6: clk: add different DualLite MLB clock configDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock configuration. Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX5: Add S/PDIF clocksPhilipp Zabel2013-06-171-1/+27
| | | | | | | | | This patch adds the S/PDIF clocks for i.MX51 and i.MX53. Tested on i.MX53. The i.MX51 has a second set of spdif_root clock dividers, and on i.MX53 there is an additional input to the spdif_xtal mux. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX53: Add SATA clockSascha Hauer2013-06-171-1/+2
| | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: clk: add the eim_slow clockHuang Shijie2013-06-171-1/+2
| | | | | | | Add the eim_slow clock, since the weim needs it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: remove MLB PLL from pllv3Jiada Wang2013-06-172-11/+0
| | | | | | | | | MLB PLL should be handled internally in MLB driver, so remove it from pllv3. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: disable pll8_mlb in mx6q_clksJiada Wang2013-06-171-1/+0
| | | | | | | | | | | The MLB PLL clock's operation doesn't fit for clock framework and it should be handled internally in MLB driver. Remove initialization of pll8_mlb clock device but leave its declaration in mx6q_clks to avoid affecting imx6q clock numbering. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: add initial support for imx6slShawn Guo2013-06-174-0/+72
| | | | | | Add initial support for i.MX6 SoloLite. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: add clock support for imx6slShawn Guo2013-06-171-0/+270
| | | | | | | | | Add clock support for i.MX6 SoloLite. It uses the dtc marco support to define all clock IDs in imx6sl-clock.h, which will be included by both clock driver and device tree sources, so that the data will stay sync all the time between kernel and DT. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: create mxc_arch_reset_init_dt() for DT bootShawn Guo2013-06-177-9/+26
| | | | | | | | | | The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to get clock. It's suitable for non-DT boot but not for DT boot where dynamic mapping and of_clk_get() should be used instead. Create mxc_arch_reset_init_dt() as the DT variant of mxc_arch_reset_init(), and change DT platforms to use it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: move clk_prepare() out from mxc_restart()Shawn Guo2013-06-1712-18/+39
| | | | | | | | | | | | | | | It's inappropriate to call clk_prepare() in mxc_restart(), because the restart routine could be called in atomic context. Move clk_get() and clk_prepare() into mxc_arch_reset_init() and only have the atomic part clk_enable() be called in mxc_restart(). As a result, mxc_arch_reset_init() needs to be called after clk gets initialized. While there, it also changes printk(KERN_ERR ...) to pr_err() and adds __init annotation for mxc_arch_reset_init(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: include <asm/io.h> in hardware.hShawn Guo2013-06-171-0/+1
| | | | | | | As IOMEM is referenced in hardware.h, <asm/io.h> should be included there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6: clk: add i.MX6 DualLite differencesDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and moves the gpu2_core configuration at that place. Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences by using cpu_is_mx6dl(). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: i.MX6: add i.MX6 specific L2 cache configurationDirk Behme2013-06-171-1/+35
| | | | | | | | | | | | | | | | | | | | | | | To improve the performance and power consumption add an i.MX6 specific L2 cache initialization. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] with two additional improvements: a) The L2X0_POWER_CTRL has only the two bits we set. So no need to read the register before. Remove the register read done in Freescale's patch. b) In the L2X0_PREFETCH_CTRL register, besides the double linefill (bit[30]), additionally enable the instruction and data prefetch (bit[29-28]). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
* ARM: i.MX5: Allow DT clock providersMartin Fuzzey2013-06-173-36/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently clock providers defined in the DT are not registered on i.MX5 platforms since of_clk_init() is not called. This is not a problem for the SOC's own clocks, which are registered in code, but prevents the DT being used to define clocks for external hardware. Fix this by calling of_clk_init() and actually using the DT to obtain the 4 SOC fixed clocks. These are already defined in the DT but were previously just used to manually obtain the rate. Fall back to the old scheme for non DT platforms. Since the same method may be useful for other i.MX platforms implement the imx_obtain_fixed_clock() function in common code. Actually changing other i.MX platforms to use this should be done later by someone with access to the appropriate hardware. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: clk-imx6q: AXI clock select index is incorrectAnson Huang2013-06-031-1/+1
| | | | | | | | | | | | The AXI clock mux should be as below: 00: periph; 01: pll2_pfd2_396m; 10: periph; 11: pll3_pfd1_540m; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: fix for ldb_di_selsJiada Wang2013-05-231-1/+1
| | | | | | | | | | As pll5_video_div has been introduced to represent the clock generated from post-divider for video. Instead of pll5_video, pll5_video_div should be proper root clock for ldb_di_sel. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: fix typo in gpu3d_shader_selsShawn Guo2013-05-121-1/+1
| | | | | | | | There is no clock pll2_pfd9_720m. Instead it should be pll3_pfd0_720m. Fix the typo in gpu3d_shader_sels. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* ARM: imx: replicate the diagnostic register of boot cpu into secondary coresShawn Guo2013-05-122-0/+26
| | | | | | | | | | | | The diagnostic register holds the errata bits. Mostly bootloader does not bring up secondary cores, so that when errata bits are set in bootloader, they are set only for boot cpu. But on a SMP configuration, it should be equally done on every single core. Set up the diagnostic register for secondary cores by replicating the register from boot cpu. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* ARM i.MX6: correct MLB clock configurationDirk Behme2013-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | According to the i.MX6 Dual/Quad technical reference manual (Figure 18-2. Clock Tree - Part 1) the MLB clock is directly feed by the AXI_CLK_ROOT. This is called 'axi' in our code. Note that the clock of the MLB IP block on the i.MX6 is completely independent of the PLL8 (MLB PLL). The MLB PLL isn't responsible for feeding the MLB IP block with a clock. Instead, it's used internally by the MLB module to sync the bus clock in case the MLB 6-pin interface is enabled: MediaLB Control 0 Register, MLB150_MLBC0[5], MLBPEN: 1 MediaLB 6-pin interface enabled. MLB PLL and MLB PHY is enabled in this case. I.e. the PLL8 MLB PLL has to be handled by the MLB driver and isn't needed for clocking the MLB module itself. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jiada Wang <Jiada_Wang@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocksPhilipp Zabel2013-05-121-3/+4
| | | | | | | | The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/ pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: Select GENERIC_ALLOCATORFabio Estevam2013-05-093-78/+1
| | | | | | | | | | | | | | | | | | | Since commit 657eee7 (media: coda: use genalloc API) the following build error happens with imx_v4_v5_defconfig: drivers/built-in.o: In function 'coda_remove': clk-composite.c:(.text+0x112180): undefined reference to 'gen_pool_free' drivers/built-in.o: In function 'coda_probe': clk-composite.c:(.text+0x112310): undefined reference to 'of_get_named_gen_pool' clk-composite.c:(.text+0x1123f4): undefined reference to 'gen_pool_alloc' clk-composite.c:(.text+0x11240c): undefined reference to 'gen_pool_virt_to_phys' clk-composite.c:(.text+0x112458): undefined reference to 'dev_get_gen_pool' Select GENERIC_ALLOCATOR and get rid of the custom IRAM_ALLOC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: imx: compile fix for hotplug.cShawn Guo2013-05-092-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit bca7a5a (ARM: cpu hotplug: remove majority of cache flushing from platforms) removes include of <asm/cacheflush.h> and hence discovers a few indirect inclusion and declaration problems as below. CC arch/arm/mach-imx/hotplug.o In file included from arch/arm/mach-imx/hotplug.c:16:0: arch/arm/mach-imx/common.h:100:29: warning: ‘struct pt_regs’ declared inside parameter list [enabled by default] arch/arm/mach-imx/common.h:100:29: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] arch/arm/mach-imx/common.h:101:29: warning: ‘struct pt_regs’ declared inside parameter list [enabled by default] arch/arm/mach-imx/hotplug.c: In function ‘imx_cpu_die’: arch/arm/mach-imx/hotplug.c:53:2: error: implicit declaration of function ‘cpu_do_idle’ [-Werror=implicit-function-declaration] arch/arm/mach-imx/hotplug.c: In function ‘imx_cpu_kill’: arch/arm/mach-imx/hotplug.c:58:26: error: ‘jiffies’ undeclared (first use in this function) arch/arm/mach-imx/hotplug.c:58:26: note: each undeclared identifier is reported only once for each function it appears in arch/arm/mach-imx/hotplug.c:58:2: error: implicit declaration of function ‘msecs_to_jiffies’ [-Werror=implicit-function-declaration] arch/arm/mach-imx/hotplug.c:61:3: error: implicit declaration of function ‘time_after’ [-Werror=implicit-function-declaration] Fix them by adding the needed inclusion and declaration. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge branch 'late/fixes' into fixesOlof Johansson2013-05-091-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * late/fixes: ARM: OMAP2+: Fix unmet direct dependencies for SERIAL_OMAP ARM: ux500: always select ABX500_CORE ARM: SIRF: select SMP_ON_UP only on SMP builds ARM: SPEAr: conditionalize l2x0 support ARM: imx: build CPU suspend code only when needed ARM: OMAP: build SMP code only for OMAP4/5 ARM: tegra: Tegra114 needs CPU_FREQ_TABLE ARM: default machine descriptor for multiplatform Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: imx: build CPU suspend code only when neededArnd Bergmann2013-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARM CPU suspend function has its own configuration symbol, which we need to use for conditionalizing any code calling into it as well. arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume': /git/arm-soc/arch/arm/mach-imx/headsmp.S:57: undefined reference to `cpu_resume' Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | Merge tag 'soc-for-linus-3' of ↵Linus Torvalds2013-05-0714-82/+444
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates (part 3) from Arnd Bergmann: "This is the third and smallest of the SoC specific updates. Changes include: - SMP support for the Xilinx zynq platform - Smaller imx changes - LPAE support for mvebu - Moving the orion5x, kirkwood, dove and mvebu platforms to a common "mbus" driver for their internal devices. It would be good to get feedback on the location of the "mbus" driver. Since this is used on multiple platforms may potentially get shared with other architectures (powerpc and arm64), it was moved to drivers/bus/. We expect other similar drivers to get moved to the same place in order to avoid creating more top-level directories under drivers/ or cluttering up the messy drivers/misc/ even more." * tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) ARM: imx: reset_controller may be disabled ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock ARM i.MX53: tve_di clock is not part of the CCM, but of TVE ARM i.MX53: make tve_ext_sel propagate rate change to PLL ARM i.MX53: Remove unused tve_gate clkdev entry ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree ARM: i.MX5: Add PATA and SRTC clocks ARM: imx: do not bring up unavailable cores ARM: imx: add initial imx6dl support ARM: imx1: mm: add call to mxc_device_init ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS ...
| * | ARM: imx: reset_controller may be disabledArnd Bergmann2013-05-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new reset controller API is optional, so if that is disabled, we must not call it from platform code. arch/arm/mach-imx/built-in.o: In function `imx_src_init': /git/arm-soc/arch/arm/mach-imx/src.c:144: undefined reference to `reset_controller_register' Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | Merge tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Olof Johansson2013-04-1330-610/+475
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc2 From Shawn Guo: The imx soc changes for 3.10: * Enable anatop, well bisa and RBC for suspend to optimize the power consumption a little bit * Clock changes for TVE, LDB, PATA, SRTC support * Add System Reset Controller (SRC) support for imx5 and imx6 * Add initial imx6dl support based on imx6q code * Kconfig for cpufreq-cpu0, defconfig updates and few other changes * tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (275 commits) ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock ARM i.MX53: tve_di clock is not part of the CCM, but of TVE ARM i.MX53: make tve_ext_sel propagate rate change to PLL ARM i.MX53: Remove unused tve_gate clkdev entry ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree ARM: i.MX5: Add PATA and SRTC clocks ARM: imx: do not bring up unavailable cores ARM: imx: add initial imx6dl support ARM: imx1: mm: add call to mxc_device_init ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS ARM: i.MX53 Add the cko1, cko2 clock outputs. staging: drm/imx: Use SRC to reset IPU ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC) ARM: imx: do not use regmap_read for ANADIG_DIGPROG ARM i.MX6q: set the LDB serial clock parent to the video PLL ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1 ARM i.MX6q: fix ldb di divider and selector clocks ARM i.MX53: fix ldb di divider and selector clocks ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags ... Signed-off-by: Olof Johansson <olof@lixom.net> Trivial change/change conflict in arch/arm/mach-imx/mach-imx6q.c resolved.
| | * | ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clockPhilipp Zabel2013-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use imx_clk_mux_flags to set the appropriate flags for the TVE selector clock. This is needed so tve_clk rate changes can propagate up to pll4_sw. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM i.MX53: tve_di clock is not part of the CCM, but of TVEPhilipp Zabel2013-04-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the tve_di clock from the CCM clock tree. It will be provided by the Television Encoder driver, as this clock is an output signal of the TVE module. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM i.MX53: make tve_ext_sel propagate rate change to PLLPhilipp Zabel2013-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed so the Television Encoder driver can set the rate on tve_clk and have it propagated up to pll4_sw. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM i.MX53: Remove unused tve_gate clkdev entryPhilipp Zabel2013-04-121-1/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM i.MX5: Remove tve_sel clock from i.MX53 clock treePhilipp Zabel2013-04-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX53, there is only tve_ext_sel. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: i.MX5: Add PATA and SRTC clocksSascha Hauer2013-04-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the clock gates and the binding documentation for PATA and SRTC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: imx: do not bring up unavailable coresShawn Guo2013-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6 Quad can be fused as i.MX6 Dual chip, and similarly i.MX6 DualLite can be fused as i.MX6 Solo. The actual number of available cores can be found out from SCU. Since we do not reflect the fusing thing in device tree, the function arm_dt_init_cpu_maps() will always call set_cpu_possible(true) for 4 cores on i.MX6 Quad/Dual and 2 cores for i.MX6 DualLite/Solo. This causes failures when kernel tries to bring those unavailable cores online. For example, the following failure message will be seen when booting an i.MX6 Solo chip. CPU1: failed to come online Though kernel will still boot fine, the message is somehow annoying. Let's get rid of it by calling set_cpu_possible(false) on those unavailable cores. While at it, the set_cpu_possible(true) for available cores is removed, since it's already been done in arm_dt_init_cpu_maps(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: imx: add initial imx6dl supportShawn Guo2013-04-124-11/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly compatible with i.MX6 Quad/Dual. And that's why we choose to support it using imx6q code with cpu_is_imx6dl() check when necessary. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: imx1: mm: add call to mxc_device_initGwenhael Goavec-Merou2013-04-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mxc_device_init() is mandatory for mxc_aips and mxc_ahb bus registration, needed as parents, at least, for gpio and dma. Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: i.MX53 Add the cko1, cko2 clock outputs.Martin Fuzzey2013-04-121-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These two clocks connect to external pins and can be muxed to various internal clocks. They are typically used either for debugging or to provide clocks to external chips (eg audio codecs). Currently only the selectable clocks that already exist in the clock tree have been added. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller ↵Philipp Zabel2013-04-122-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (SRC) The SRC has auto-deasserting reset bits that control reset lines to the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset controller that can be controlled by those devices using the reset controller API. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: imx: do not use regmap_read for ANADIG_DIGPROGShawn Guo2013-04-122-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function imx_anatop_get_digprog() that reads register ANADIG_DIGPROG is called to identify silicon version. Users might query silicon version earlier than regmap subsystem is ready. For example, imx6q clock driver query revision in mx6q_clocks_init(), where regmap is not initialized yet. Change imx_anatop_get_digprog() to map anatop block and read ANADIG_DIGPROG in the native way, so that the function can work at very early stage. While at it, let's move imx_print_silicon_rev() back to imx6q_timer_init() to have the message show up a little earlier. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM i.MX6q: set the LDB serial clock parent to the video PLLPhilipp Zabel2013-04-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX6q revision 1.1 and later, set the video PLL as parent for the LDB clock branch. On revision 1.0, the video PLL is useless due to missing dividers, so keep the default parent (mmdc_ch1_axi). Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-04 06:46:16 +0100