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* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-0728-87/+87
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove asm/hardware.h, use asm/arch/hardware.h insteadRussell King2008-08-078-8/+8
| | | | | | | | | Remove includes of asm/hardware.h in addition to asm/arch/hardware.h. Then, since asm/hardware.h only exists to include asm/arch/hardware.h, update everything to directly include asm/arch/hardware.h and remove asm/hardware.h. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Eliminate useless includes of asm/mach-types.hRussell King2008-08-071-1/+0
| | | | | | | | There are 43 includes of asm/mach-types.h by files that don't reference anything from that file. Remove these unnecessary includes. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5179/1: Replace obsolete IRQT_* and __IRQT_* values with IRQ_TYPE_*Dmitry Baryshkov2008-07-271-3/+3
| | | | | | | | | | | | | | | | | | | | IRQT_* and __IRQT_* were obsoleted long ago by patch [3692/1]. Remove them completely. Sed script for the reference: s/__IRQT_RISEDGE/IRQ_TYPE_EDGE_RISING/g s/__IRQT_FALEDGE/IRQ_TYPE_EDGE_FALLING/g s/__IRQT_LOWLVL/IRQ_TYPE_LEVEL_LOW/g s/__IRQT_HIGHLVL/IRQ_TYPE_LEVEL_HIGH/g s/IRQT_RISING/IRQ_TYPE_EDGE_RISING/g s/IRQT_FALLING/IRQ_TYPE_EDGE_FALLING/g s/IRQT_BOTHEDGE/IRQ_TYPE_EDGE_BOTH/g s/IRQT_LOW/IRQ_TYPE_LEVEL_LOW/g s/IRQT_HIGH/IRQ_TYPE_LEVEL_HIGH/g s/IRQT_PROBE/IRQ_TYPE_PROBE/g s/IRQT_NOEDGE/IRQ_TYPE_NONE/g Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
*---. Merge branches 'at91', 'dyntick', 'ep93xx', 'iop', 'ixp', 'misc', 'orion', ↵Russell King2008-07-1023-206/+1570
|\ \ \ | | | | | | | | | | | | 'omap-reviewed', 'rpc', 'rtc' and 's3c' into devel
| | | * ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithmPaul Walmsley2008-07-035-18/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new rate rounding algorithm for DPLL clocks on the OMAP2/3 architecture. For a desired DPLL target rate, there may be several multiplier/divider (M, N) values which will generate a sufficiently close rate. Lower N values result in greater power economy. However, lower N values can cause the difference between the rounded rate and the target rate ("rate error") to be larger than it would be with a higher N. This can cause downstream devices to run more slowly than they otherwise would. This DPLL rate rounding algorithm: - attempts to find the lowest possible N (DPLL divider) to reach the target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>, lower N values save more power than higher N values). - allows developers to set an upper bound on the error between the rounded rate and the desired target rate ("rate tolerance"), so an appropriate balance between rate fidelity and power savings can be set. This maximum rate error tolerance is set via omap2_set_dpll_rate_tolerance(). - never returns a rounded rate higher than the target rate. The rate rounding algorithm caches the last rounded M, N, and rate computation to avoid rounding the rate twice for each clk_set_rate() call. (This patch does not yet implement set_rate for DPLLs; that follows in a future patch.) The algorithm trades execution speed for rate accuracy. It will find the (M, N) set that results in the least rate error, within a specified rate tolerance. It does this by evaluating each divider setting - on OMAP3, this involves 128 steps. Another approach to DPLL rate rounding would be to bail out as soon as a valid rate is found within the rate tolerance, which would trade rate accuracy for execution speed. Alternate implementations welcome. This code is not yet used by the OMAP24XX DPLL clock, since it is currently defined as a composite clock, fusing the DPLL M,N and the M2 output divider. This patch also renames the existing OMAP24xx DPLL programming functions to highlight that they program both the DPLL and the DPLL's output multiplier. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2: Clock: Add OMAP3 DPLL autoidle functionsPaul Walmsley2008-07-034-30/+371
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for DPLL autoidle control to the OMAP3 clock framework. These functions will be used by the noncore DPLL enable and disable code - this is because, according to the CDP code, the DPLL autoidle status must be saved and restored across DPLL lock/bypass/off transitions. N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather than just two. This code currently does not support the third option, low-power bypass autoidle. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Add OMAP chip type structure; clean up mach-omap2/id.cPaul Walmsley2008-07-031-27/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new OMAP chip identification interface, omap_chip_id. omap_chip_id is a structure which contains one bit for each OMAP2/3 CPU type, and on 3430, ES level. For example, the CHIP_IS_OMAP2420 bit is set in omap_chip at boot on an OMAP2420. On OMAP3430ES2, both CHIP_IS_OMAP3430 and CHIP_IS_OMAP3430ES2 bits are set. omap_chip is set in mach-omap2/id.c by _set_omap_chip(). Other code should use the omap_chip_is() function to test against omap_chip. Also, clean up id.c by splitting some code out of omap_check_revision() into its own function, _set_system_rev(); and converting some debug printk()s into pr_debug(). Second revision. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Turn CM and PRM access into functionsTony Lindgren2008-07-034-7/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise compiling in omap2 and omap3 will not work. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Introduce omap_globals and prcm access functions for multi-omapTony Lindgren2008-07-037-46/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New struct omap_globals contains the omap processor specific module bases. Use omap_globals to set the various base addresses to make detecting omap chip type simpler. Also introduce OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS for future multi-omap patches. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: McBSP: Add support for mcbsp on mach-omap2Eduardo Valentin2008-07-033-10/+230
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for mach-omap2 based on current mcbsp platform driver. Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: McBSP: Add support for mcbsp on mach-omap1Eduardo Valentin2008-07-031-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for mach-omap1 based on current mcbsp platform driver. Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: SRAM: Split sram24xx.S into sram242x.S and sram243x.STony Lindgren2008-07-036-57/+397
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Split sram24xx.S into sram242x.S and sram243x.S Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: SRAM: Move omap2 sram-fn.S to sram242x.STony Lindgren2008-07-032-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file will get split between sram242x.S and sram243x.S in following patch. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: DMTimer: Optimize by adding load and startRichard Woodruff2008-07-031-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch optimizes the timer load and start sequence. By combining the load and start a needless posted wait can be removed from the system timer execution path. * Before patch register writes are taking up .078% @ 500MHz during idle. Address |total |min |max |avr |count|ratio% old\process\default_idle|7.369s |0.0us|999.902ms|14.477ms|509. |62.661% ld\Global\cpu_v7_do_idle|4.265s |0.0us|375.786ms|24.374ms|175. |36.270% (UNKNOWN)|17.503ms|0.us|531.080us|5.119us|3419. |0.148% r\omap_dm_timer_set_load|8.135ms|0.0us|79.887us|15.065us|540. |0.069% <-- \vmlinux-old\Global\_end|2.023ms|0.0us|4.000us|0.560us|3613. |0.017% -old\Global\__raw_readsw|1.962ms|0.0us|108.610us|9.167us|214. |0.016% old\smc91x\smc_interrupt|1.353ms|0.0us|10.212us|2.348us|576. |0.011% s/namei\__link_path_walk|1.161ms|0.0us|4.310us|0.762us| 1524. |0.009% \omap_dm_timer_write_reg|1.085ms|0.0us|126.150us|2.153us|504. |0.009% <-- * After patch timer functions do not show up in top listings for long captures. Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Correcting the gpmc prefetch control register addressThara Gopinath2008-06-071-1/+1
| |_|/ |/| | | | | | | | | | | | | | Correcting the GPMC_PREFETCH_CONTROL register address Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | [ARM] dyntick: Remove obsolete and unused ARM dyntick supportRussell King2008-05-121-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | dyntick is superseded by the clocksource/clockevent infrastructure, using the NO_HZ configuration option. No one implements dyntick on ARM anymore, so it's pointless keeping it around. Remove dyntick support. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: OMAP: Fixed comments on global PRM register usageKalle Jokiniemi2008-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | Fixed comments on global PRM register usage. Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | ARM: OMAP: Add PARENT_CONTROLS_CLOCK flag to dpll5_m2_ckHögander Jouni2008-05-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes following message on dpll5_m2_ck enable and disable: clock.c: Enable for dpll5_m2_ck without enable code clock: clk_disable called on independent clock dpll5_m2_ck which has no enable_reg Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | ARM: OMAP: PRCM fixes to ssi clock handlingJouni Högander2008-05-092-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | ssi_l4_ick should have PARENT_CONTROLS_CLOCK flag. ST_SSI_STDBY bit in idlest register cannot be used in omap2_clk_wait_ready Signed-off-by: Jouni Högander <jouni.hogander@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | ARM: OMAP: Add fuctional clock enabler for iva2Hiroshi DOYU2008-05-092-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add fuctional clock enabler for iva2 Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | ARM: OMAP: Fix 34xx to use correct shift values for gpio2-6 fclksJouni Högander2008-05-091-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Wrong shift values were used for gpio2-6 fclks (gpt2-6 shift). Signed-off-by: Jouni Högander <jouni.hogander@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | ARM: OMAP: Fix Unbalanced enable for IRQ in omap mailboxHiroshi DOYU2008-05-091-10/+15
| | | | | | | | | | | | | | | Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | ARM: OMAP: Add calls to omap2_set_globals_*()Paul Walmsley2008-05-094-0/+4
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | Add the omap2_set_globals_{242x,243x,343x}() functions. These functions are called early upon boot in the map_io() functions in the board-specific init files. This patch was accidentally left out of the earlier series. This fixes omap2 booting as noted by Kyungmin Park <kmpark@infradead.org>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kyungmin Park <kmpark@infradead.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: New DPLL clock frameworkRoman Tereshonkov2008-04-144-109/+410
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These changes is the result of the discussion with Paul Walmsley. His ideas are included into this patch. Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks, and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk). omap2_get_dpll_rate() now returns the correct DPLL rate, as represented by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along with high-frequency bypass support. Add support for DPLLs function in locked and bypass clock modes. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Add 34xx clock codePaul Walmsley2008-04-142-0/+236
| | | | | | | | | | | | | | | | | | This patch add 34xx clock code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Add 34xx clocksPaul Walmsley2008-04-141-0/+2704
| | | | | | | | | | | | | | | | | | This patch defines 34xx clocks. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Remove old PRCM register access codePaul Walmsley2008-04-143-797/+1
| | | | | | | | | | | | | | | | | | Remove old PRCM register access code that is no longer needed. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Clean up 24xx clock codeTony Lindgren2008-04-144-62/+49
| | | | | | | | | | | | | | | | Clean up 24xx clock code to sync it with linux-omap tree. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Remove old 24xx specific clock functionsPaul Walmsley2008-04-141-722/+0
| | | | | | | | | | | | | | Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP: Add rest of 24xx clocksPaul Walmsley2008-04-141-530/+957
| | | | | | | | | | | | | | | | | | This patch adds the rest of clocks for 24xx. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Change 24xx to use shared clock code and new reg accessPaul Walmsley2008-04-146-226/+467
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes 24xx to use shared clock code and new register access. Note that patch adds some temporary OLD_CK defines to keep patch more readable. These temporary defines will be removed in the next patch. Also not all clocks are changed in this patch to limit the size. Also, the patch fixes few incorrect clock defines in clock24xx.h. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Add common clock framework for 24xx and 34xxPaul Walmsley2008-04-142-0/+830
| | | | | | | | | | | | | | | | | | | | This patch adds a common clock framework for 24xx and 34xx. Note that this patch does not add it to Makefile until in next patch. Some functions are modified from earlier 24xx clock framework code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Move clock.c to clock24xx.cPaul Walmsley2008-04-142-1/+4
| | | | | | | | | | | | | | | | | | | | | | This patch moves clock.h to clock24xx.c to make room for adding common clock code for 24xx and 34xx. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Move clock.h to clock24xx.hPaul Walmsley2008-04-142-1/+1
| | | | | | | | | | | | | | | | | | | | This patch moves clock.h to clock24xx.h to make room for adding common clock code for 24xx and 34xx. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Remove old 24xx PM codeTony Lindgren2008-04-141-269/+1
| | | | | | | | | | | | | | | | | | | | | | This patch removes old 24xx PM code that does not really work for sleep states, and uses old power management register access. Working PM code will be added later. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Change 24xx to use new register accessPaul Walmsley2008-04-1410-97/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Add register access for 34xxTony Lindgren2008-04-142-0/+1251
| | | | | | | | | | | | | | | | | | This patch adds register access for 34xx power and clock management. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Add common register access for 24xx and 34xxPaul Walmsley2008-04-148-2/+1571
| | | | | | | | | | | | | | | | | | | | | | This patch adds common register access for 24xx and 34xx power and clock management in order to share code between 24xx and 34xx. Only change USB platform init code to use new register access, other access will be changed in later patches. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Clean-up mux codeTony Lindgren2008-04-141-26/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | Misc clean-up for the mux code and remove some unnecessary ifdefs. Patch changes debug function so it can be used on both 24xx and 34xx. Changes are mostly for omap2, but patch also cleans up some omap1 and common mux code. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP2: Add new pin multiplexing configurationsTony Lindgren2008-04-141-3/+41
| | | | | | | | | | | | | | | | Add new pin multiplexing configurations Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP: Timer32K: Re-organize duplicated 32k-timer codeKevin Hilman2008-04-142-18/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP2/3, the gp-timer code can be used for a 32kHz timer simply by setting the source to be the 32k clock instead of sys_clk. This patch uses the mach-omap2/timer-gp.c code for 32kHz timer on OMAP2, moving the logic into mach-omap2/timer-gp.c, and not using plat-omap/timer32k.c which, for OMAP2, is redundant with the timer-gp code. Also, if CONFIG_OMAP_32K_TIMER is enabled, the gptimer-based clocksource is not used. Instead the default 32k sync counter is used as the clocksource (see the clocksource in plat-omap/common.c.) This is important for sleep/suspend so there is a valid counter during sleep. Note that the suspend/sleep code needs fixing to check for overflows of this counter. In addition, the OMAP2/3 details are removed from timer32k.c leaving that with only OMAP1 specifics. A follow-up patch will move it from plat-omap common code to mach-omap1. Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP: Split omap_cfg_reg() into omap processor specific functionsTony Lindgren2008-04-141-0/+31
| | | | | | | | | | | | | | | | | | | | Use omap processor specific function depending on system type. Based on an earlier patch by Klaus Pedersen <klaus.k.pedersen@nokia.com>. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP: Allow registering pin mux functionTony Lindgren2008-04-141-2/+19
|/ | | | | | | | | | | | | This patch changes pin multiplexing init to allow registering custom function. The omap_cfg_reg() func will be split into omap processor specific functions in later patch. This is done to make adding omap3 pin multiplexing easier. Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Register the L4 io bus to boot OMAP2Kyungmin Park2008-03-061-0/+6
| | | | | | | This patch enables OMAP2 to boot. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'pxa-plat' into develRussell King2008-01-282-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pxa-plat: (53 commits) [ARM] 4762/1: Basic support for Toradex Colibri module [ARM] pxa: fix mci_init functions returning -1 [ARM] 4737/1: Refactor corgi_lcd to improve readability + bugfix [ARM] 4747/1: pcm027: support for pcm990 baseboard for phyCORE-PXA270 [ARM] 4746/1: pcm027: network support for phyCORE-PXA270 [ARM] 4745/1: pcm027: default configuration [ARM] 4744/1: pcm027: add support for phyCORE-PXA270 CPU module [NET] smc91x: Make smc91x use IRQ resource trigger flags [ARM] pxa: add default config for littleton [ARM] pxa: add basic support for Littleton (PXA3xx Form Factor Platform) [ARM] 4664/1: Add basic support for HTC Magician PDA phones [ARM] 4649/1: Base support for pxa-based Toshiba e-series PDAs. [ARM] pxa: skip registers saving/restoring if entering standby mode [ARM] pxa: fix PXA27x resume [ARM] pxa: Avoid fiddling with CKEN register on suspend [ARM] pxa: Add PXA3 standby code hooked into the IRQ wake scheme [ARM] pxa: Add zylonite MFP wakeup configurations [ARM] pxa: program MFPs for low power mode when suspending [ARM] pxa: make MFP configuration processor independent [ARM] pxa: remove un-used pxa3xx_mfp_set_xxx() functions ... Conflicts: arch/arm/mach-pxa/ssp.c Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [NET] smc91x: Make smc91x use IRQ resource trigger flagsRussell King2008-01-282-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | smc91x is shared between many different platforms. Each platform needs to specify the interrupt type, and in some cases the irq type depends on more than just the build configuration - it depends on runtime checks. Rather than throwing this code into the SMC_IRQ_FLAGS definition, provide a way for these flags to be passed via the IRQ resource itself. Note that IRQF_TRIGGER_* constants are intentionally defined to correspond with the IORESOURCE_IRQ_* interrupt type flags, in much the same way that the low bits of PCI iomem resources correspond with the BAR flag bits. Also provide a way to configure smc91x to read the IRQ flags from the resource. Once all platforms have been converted over (signified by all definitions of SMC_IRQ_FLAGS being -1) SMC_IRQ_FLAGS should be removed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Nicolas Pitre <nico@cam.org> Acked-by: Jeff Garzik <jgarzik@redhat.com>
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*-. \ Merge branches 'at91', 'ep93xx', 'iop', 'kprobes', 'ks8695', 'misc', 'msm', ↵Russell King2008-01-281-1/+0
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 's3c2410', 'sa1100' and 'vfp' into devel * at91: (24 commits) [ARM] 4615/4: sam926[13]ek buttons updated [ARM] 4765/1: [AT91] AT91CAP9A-DK board support [ARM] 4764/1: [AT91] AT91CAP9 core support [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation [ARM] 4761/1: [AT91] Board-support for NEW_LEDs [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200 [ARM] 4759/1: [AT91] Buttons on CSB300 [ARM] 4758/1: [AT91] LEDs [ARM] 4757/1: [AT91] UART initialization [ARM] 4756/1: [AT91] Makefile cleanup [ARM] 4755/1: [AT91] NAND update [ARM] 4754/1: [AT91] SSC library support [ARM] 4753/1: [AT91] Use DMA_BIT_MASK [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9 [ARM] 4751/1: [AT91] ISI peripheral on SAM9263 [ARM] 4750/1: [AT91] STN LCD displays on SAM9261 [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY [ARM] 4646/1: AT91: configurable HZ, default to 128 [ARM] 4688/1: at91: speed-up irq processing [ARM] 4657/1: AT91: Header definition update ... * ep93xx: [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups [ARM] 4668/1: ep93xx: implement new GPIO API * iop: [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device [ARM] 4708/1: iop: update defconfigs for 2.6.24 * kprobes: ARM kprobes: let's enable it ARM kprobes: special hook for the kprobes breakpoint handler ARM kprobes: prevent some functions involved with kprobes from being probed ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack ARM kprobes: add the kprobes hook to the page fault handler ARM kprobes: core code ARM kprobes: instruction single-stepping support * ks8695: [ARM] 4603/1: KS8695: debugfs interface to view pin state [ARM] 4601/1: KS8695: PCI support * misc: [ARM] remove duplicate includes [ARM] CONFIG_DEBUG_STACK_USAGE [ARM] 4689/1: small comment wrap fix [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS [SERIAL] 21285: Report baud rate back via termios [ARM] Remove pointless casts from void pointers, [ARM] Misc minor interrupt handler cleanups [ARM] Remove at91_lcdc.h [ARM] ARRAY_SIZE() cleanup [ARM] Update mach-types * msm: [ARM] msm: dma support for MSM7X00A [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A) [ARM] msm: irq and timer support for ARCH_MSM7X00A [ARM] msm: core platform support for ARCH_MSM7X00A * s3c2410: (33 commits) [ARM] 4795/1: S3C244X: Add armclk and setparent call [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk [ARM] 4790/1: S3C2412: Fix parent selection for msysclk. [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used. [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull() [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users [ARM] 4781/1: S3C24XX: DMA suspend and resume support [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call [ARM] 4778/1: S3C2412: Add armclk and init from DVS state [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected ... * sa1100: [ARM] sa1100: add clock source support * vfp: [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support [ARM] 4583/1: ARMv7: Add VFPv3 support [ARM] 4582/2: Add support for the common VFP subarchitecture
| | * [ARM] remove duplicate includesLucas Woods2008-01-261-1/+0
| |/ | | | | | | | | | | | | Signed-off-by: Lucas Woods <woodzy@gmail.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* / [ARM] Fix timer damage from d3d74453c34f8fd87674a8cf5b8a327c68f22e99Russell King2008-01-281-4/+0
|/ | | | | | | | | | | Move the xtime write mode seqlock into timer_tick(), so it only surrounds the call to do_timer(). This avoids a deadlock in update_process_times() ... hrtimer_get_softirq_time() which tries to get a read mode seqlock on xtime, thereby preventing booting. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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