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* irqchip/sun6i-r: Use a stacked irqchip driverSamuel Holland2021-01-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the original sun4i interrupt controller than the sun7i/sun9i NMI controller. It is used for two distinct purposes: - To control the trigger, latch, and mask for the NMI input pin - To provide the interrupt input for the ARISC coprocessor As this interrupt controller is not documented, information about it comes from vendor-provided firmware blobs and from experimentation. Differences from the sun4i interrupt controller appear to be: - It only has one or two registers of each kind (max 32 or 64 IRQs) - Multiplexing logic is added to support additional inputs - There is no FIQ-related logic - There is no interrupt priority logic In order to fulfill its two purposes, this hardware block combines four types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0 pending" output from this chip, if enabled, is then routed to a SPI IRQ input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect the NMI IRQ seen at the GIC. The NMI is followed by a contiguous block of 15 "direct" (my name for them) IRQ inputs that are connected in parallel to both R_INTC and the GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the IRQs seen at the GIC. Following the direct IRQs are the ARISC's copy of banked IRQs for shared peripherals. These are not relevant to Linux. The remaining IRQs are connected to a multiplexer and provide access to the first (up to) 128 SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs. Because of the 1:1 correspondence between R_INTC and GIC inputs, this is a perfect scenario for using a stacked irqchip driver. We want to hook into setting the NMI trigger type, but not actually handle any IRQ here. To allow access to all multiplexed IRQs, this driver requires a new binding where the interrupt number matches the GIC interrupt number. (This moves the NMI from number 0 to 32 or 96, depending on the SoC.) For simplicity, copy the three-cell GIC binding; this disambiguates interrupt 0 in the old binding (the NMI) from interrupt 0 in the new binding (SPI 0) by the number of cells. Since R_INTC is in the always-on power domain, and its output is visible to the power management coprocessor, a stacked irqchip driver provides a simple way to add wakeup support to any of its IRQs. That is the next patch; for now, just the NMI is moved over. This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi: Support sun6i-a31-r-intc compatible"). Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210118055040.21910-4-samuel@sholland.org
* ARM: sunxi: Add machine match for the Allwinner V3 SoCPaul Kocialkowski2020-11-021-0/+1
| | | | | | | | | | The Allwinner V3 SoC shares the same base as the V3s but comes with extra pins and features available. As a result, it has its dedicated compatible string (already used in device trees), which is added here. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201031182137.1879521-2-contact@paulk.fr
* ARM: sunxi: Replace <linux/clk-provider.h> by <linux/of_clk.h>Geert Uytterhoeven2020-02-121-1/+1
| | | | | | | | | | | The Allwinner platform code is not a clock provider, and just needs to call of_clk_init(). Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
* ARM: sunxi: Fix CPU powerdown on A83TOndrej Jirman2019-10-291-1/+5
| | | | | | | | | | | | PRCM_PWROFF_GATING_REG has CPU0 at bit 4 on A83T. So without this patch, instead of gating the CPU0, the whole cluster was power gated, when shutting down first CPU in the cluster. Fixes: 6961275e72a8c1 ("ARM: sun8i: smp: Add support for A83T") Signed-off-by: Ondrej Jirman <megous@megous.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Cc: stable@vger.kernel.org Signed-off-by: Maxime Ripard <mripard@kernel.org>
* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
| | | | | | | | | | | | | | Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: sunxi: fix a leaked reference by adding missing of_node_putWen Yang2019-03-181-0/+2
| | | | | | | | | | | | | | | | | | | The call to of_get_next_child returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./arch/arm/mach-sunxi/platsmp.c:55:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 46, but without a corresponding object release within this function. ./arch/arm/mach-sunxi/platsmp.c:138:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 129, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Russell King <linux@armlinux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: sunxi: fix a leaked reference by adding missing of_node_putWen Yang2019-03-182-1/+6
| | | | | | | | | | | | | | | | | | The call to of_get_next_child returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./arch/arm/mach-sunxi/mc_smp.c:110:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 97, but without a corresponding object release within this functio ./arch/arm/mach-sunxi/platsmp.c:138:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 129, but without a corresponding object release within this function Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Russell King <linux@armlinux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org (open list) Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* reset: sunxi: declare sun6i_reset_init in a header filePhilipp Zabel2019-01-281-1/+1
| | | | | | | | | Avoid declaring extern functions in c files. To make sure function definition and usage don't get out of sync, declare sun6i_reset_init in a common header. Suggested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* ARM: sunxi: add Allwinner ARMv5 SoCsMesih Kilinc2018-12-032-1/+21
| | | | | | | | | | Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600). Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCsMesih Kilinc2018-12-031-0/+6
| | | | | | | | | | Allwinner also has some ARMv5 SoCs. In order to add support for them, check ARM_MULTI_V7 before enabling ARMv7 SoC's. Add help text for ARCH_SUNXI menuconfig. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: sun8i: smp: Add support for A83TMylène Josserand2018-05-082-16/+137
| | | | | | | | | | | | | | | | Add the support for A83T. A83T SoC has an additional register than A80 to handle CPU configurations: R_CPUS_CFG. Information about the register comes from Allwinner's BSP driver. An important difference is the Power Off Gating register for clusters which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T. There is also a bit swap between sun8i-a83t and sun9i-a80 that must be handled. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: sun9i: smp: Add is_a83t fieldMylène Josserand2018-05-081-0/+4
| | | | | | | | | | | | To prepare the support of sun8i-a83t, add a field in the smp_data structure to know if we are on sun9i-a80 or sun8i-a83t. Add also a global variable to retrieve which architecture we are having. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: sun9i: smp: Rename clusters's power-offMylène Josserand2018-05-081-3/+3
| | | | | | | | | | | | | To prepare the support for sun8i-a83t, rename the macro that handles the power-off of clusters because it is different from sun9i-a80 to sun8i-a83t. The power off register for clusters are different from a80 and a83t. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: sunxi: Add initialization of CNTVOFFMylène Josserand2018-05-082-1/+20
| | | | | | | | | | | | | | | | | | Add the initialization of CNTVOFF for sun8i-a83t. For boot CPU, create a new machine that handles this function's call in an "init_early" callback. We need to initialize CNTVOFF before the arch timer's initialization otherwise, it will not be taken into account and fails to boot correctly. Because of that, this function can't be called in SMP's early_initcall function which is called after timer's init. For secondary CPUs, add this function into secondary_startup assembly entry. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: sunxi: smp: Move assembly code into a fileMylène Josserand2018-05-083-79/+85
| | | | | | | | | | | | Move the assembly code for cluster cache enabling and resuming into an assembly file instead of having it directly in C code. Remove the CFLAGS because we are using the ARM directive "arch" instead. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: sunxi: mc-smp: Split out SoC-specific device node lookup sequenceChen-Yu Tsai2018-03-101-40/+86
| | | | | | | | | | | | | | | The multi-cluster SMP code maps the address spaces of several hardware control blocks. The device nodes for them are SoC-specific. To help with supporting other SoCs to re-use this code, these bits should be split out to a separate function tied to the enable-method string. This patch splits out and groups the device node lookup sequence, and adds new data structures to have the newly created function tied to the enable method string. This structure can also be used to encode other differences between the SoCs. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sunxi: mc-smp: Use DT enable-method for sun9i A80 SMPChen-Yu Tsai2018-03-101-1/+20
| | | | | | | | | | | | | | | | Instead of having an early init function check the machine compatible and installing multi-cluster SMP support for the A80 if it matches, use a new cpu enable-method string. This makes the platform support future proof in case anyone manages to add PSCI support. The original init code for the SMP support is changed into the .prepare_cpus callback in the smp_operations structure. Instead of panicing when resources are missing like on some platforms, our code merely guards against engaging SMP or CPU hotplug and returns an error. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sunxi: mc-smp: Fix "lookback" typoChen-Yu Tsai2018-03-101-2/+2
| | | | | | | | | The sunxi_mc_smp_lookback function is modeled after the mcpm_loopback function in the MCPM framework. "lookback" was a typo introduced when the new function was added. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun9i: smp: Support cpu0 hotplugChen-Yu Tsai2018-02-201-3/+56
| | | | | | | | | | | | | | | | | The BROM has a branch that checks if the primary core is hotplugging. If the magic flag is set, execution jumps to the address set in the software entry register. (Secondary cores always branch to the that address.) This patch sets the flags that makes BROM jump execution on the primary core (cpu0) to the SMP software entry code when the core is powered back up. After it is re-integrated into the system, the flag is cleared. A custom .cpu_can_disable callback that returns true for all cpus, so that cpu0 can really be brought down. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun9i: smp: Support CPU/cluster power down and hotplugging for cpu1~7Chen-Yu Tsai2018-02-201-1/+189
| | | | | | | | | | | | | | This patch adds common code used to power down all cores and clusters. The code was previously based on the MCPM framework. It has now been adapted to hook into struct smp_operations directly, but the code structure still shows signs of prior work. The primary core (cpu0) requires setting flags to have the BROM bounce execution to the SMP software entry code. This is done in a subsequent patch to keep the changes cleanly separated. By default the ARM SMP code blocks cpu0 from being turned off, so splitting this out is safe. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun9i: Support SMP bring-up on A80Chen-Yu Tsai2018-02-203-0/+560
| | | | | | | | | | | | | | The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and 1 cluster of 4 Cortex-A15s. This patch adds support to bring up the second cluster and thus all cores using custom platform SMP code. Core/cluster power down has not been implemented, thus CPU hotplugging is not supported. Parts of the trampoline and re-entry code for the boot cpu was adapted from the MCPM framework. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sunxi: add support for R40 SoCIcenowy Zheng2017-09-221-0/+1
| | | | | | | | | | Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clocksource/drivers: Rename clocksource_probe to timer_probeDaniel Lezcano2017-06-141-1/+1
| | | | | | | | | | The function name is now renamed to 'timer_probe' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Select PM_OPPMaxime Ripard2017-03-061-0/+1
| | | | | | | | | Device frequency scaling is implemented through devfreq in the kernel, which requires CONFIG_PM_OPP. Let's select it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds2017-02-281-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: - nommu updates from Afzal Mohammed cleaning up the vectors support - allow DMA memory "mapping" for nommu Benjamin Gaignard - fixing a correctness issue with R_ARM_PREL31 relocations in the module linker - add strlen() prototype for the decompressor - support for DEBUG_VIRTUAL from Florian Fainelli - adjusting memory bounds after memory reservations have been registered - unipher cache handling updates from Masahiro Yamada - initrd and Thumb Kconfig cleanups * 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (23 commits) ARM: mm: round the initrd reservation to page boundaries ARM: mm: clean up initrd initialisation ARM: mm: move initrd init code out of arm_memblock_init() ARM: 8655/1: improve NOMMU definition of pgprot_*() ARM: 8654/1: decompressor: add strlen prototype ARM: 8652/1: cache-uniphier: clean up active way setup code ARM: 8651/1: cache-uniphier: include <linux/errno.h> instead of <linux/types.h> ARM: 8650/1: module: handle negative R_ARM_PREL31 addends correctly ARM: 8649/2: nommu: remove Hivecs configuration is asm ARM: 8648/2: nommu: display vectors base ARM: 8647/2: nommu: dynamic exception base address setting ARM: 8646/1: mmu: decouple VECTORS_BASE from Kconfig ARM: 8644/1: Reduce "CPU: shutdown" message to debug level ARM: 8641/1: treewide: Replace uses of virt_to_phys with __pa_symbol ARM: 8640/1: Add support for CONFIG_DEBUG_VIRTUAL ARM: 8639/1: Define KERNEL_START and KERNEL_END ARM: 8638/1: mtd: lart: Rename partition defines to be prefixed with PART_ ARM: 8637/1: Adjust memory boundaries after reservations ARM: 8636/1: Cleanup sanity_check_meminfo ARM: add CPU_THUMB_CAPABLE to indicate possible Thumb support ...
| * ARM: 8641/1: treewide: Replace uses of virt_to_phys with __pa_symbolFlorian Fainelli2017-02-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | All low-level PM/SMP code using virt_to_phys() should actually use __pa_symbol() against kernel symbols. Update code where relevant to move away from virt_to_phys(). Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Laura Abbott <labbott@redhat.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | arm: sunxi: add support for V3s SoCIcenowy Zheng2017-01-201-0/+1
| | | | | | | | | | | | | | | | Allwinner V3s is a low-end single-core Cortex-A7 SoC, with 64MB integrated DRAM, and several peripherals. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: add support for H2+ SoCIcenowy Zheng2017-01-021-0/+1
|/ | | | | | | | | | Allwinner H2+ is a quad-core Cortex-A7 SoC. It is very like H3, that they share the same SoC ID (0x1680), and H3 memory maps as well as drivers works well on the SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: Support the Nextthing GR8Maxime Ripard2016-09-081-0/+1
| | | | | | | | | | | The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family. It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S), but some controllers missing too (Ethernet, less I2C, less UARTs). Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: enable big-endianMichael Weiser2016-08-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | With previous fixes to stmmac, sun4i-emac and sun4i-mmc at least the Cubieboard2 incarnation of sunxi works correctly in big-endian mode. Allow the selection of big-endian. Tested using a Cubieboard2 DualCard and the following hardware-components: - GMAC (stmmac) - EMAC (sun4i-emac) - SATA - SPI - UART - security system - touchscreen controller hwmon functionality - pinctrl (custom interrupt for SPI ethernet controller) - watchdog as reset controller - onboard RTC - DS1307 I2C RTC - sound codec and with this indirectly the DMA engine Signed-off-by: Michael Weiser <michael.weiser@gmx.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: do away with ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIBLinus Walleij2016-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | This replaces: - "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB" as this can now be selected directly. - "select ARCH_WANT_OPTIONAL_GPIOLIB" with no dependency: GPIOLIB is now selectable by everyone, so we need not declare our intent to select it. When ordering the symbols the following rationale was used: if the selects were in alphabetical order, I moved select GPIOLIB to be in alphabetical order, but if the selects were not maintained in alphabetical order, I just replaced "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB". Cc: Michael Büsch <m@bues.ch> Cc: arm@kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* cpufreq: sunxi: Use generic platdev driverViresh Kumar2016-04-251-9/+0
| | | | | | | | | The cpufreq-dt-platdev driver supports creation of cpufreq-dt platform device now, reuse that and remove similar code from platform code. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* ARM: sunxi: Introduce Allwinner for A83T supportVishnu Patekar2016-02-051-0/+1
| | | | | | | | | | | | | | Allwinner A83T is octa-core cortex-a7 based SoC. It's clock control unit and prcm, pinmux are different from previous sun8i series. Its processor cores are arragned in two clusters 4 cores each, similar to A80. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> [maxime: Removed the clock protection code] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: use "depends on" for SoC configs instead of "if" after promptMasahiro Yamada2015-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many ARM sub-architectures use prompts followed by "if" conditional, but it is wrong. Please notice the difference between config ARCH_FOO bool "Foo SoCs" if ARCH_MULTI_V7 and config ARCH_FOO bool "Foo SoCs" depends on ARCH_MULTI_V7 These two are *not* equivalent! In the former statement, it is not ARCH_FOO, but its prompt that depends on ARCH_MULTI_V7. So, it is completely valid that ARCH_FOO is selected by another, but ARCH_MULTI_V7 is still disabled. As it is not unmet dependency, Kconfig never warns. This is probably not what you want. The former should be used only when you need to do so, and you really understand what you are doing. (In most cases, it should be wrong!) For enabling/disabling sub-architectures, the latter is always correct. As a good side effect, this commit fixes some entries over 80 columns (mach-imx, mach-integrator, mach-mbevu). [Arnd: I note that there is not really a bug here, according to the discussion that followed, but I can see value in being consistent and in making the lines shorter] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Jun Nie <jun.nie@linaro.org> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Krzysztof Halasa <khc@piap.pl> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: use const and __initconst for smp_operationsMasahiro Yamada2015-12-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | These smp_operations structures are not over-written, so add "const" qualifier and replace __initdata with __initconst. Also, add "static" where it is possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> # qcom part Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'armsoc-soc' of ↵Linus Torvalds2015-11-101-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "New and/or improved SoC support for this release: Marvell Berlin: - Enable standard DT-based cpufreq - Add CPU hotplug support Freescale: - Ethernet init for i.MX7D - Suspend/resume support for i.MX6UL Allwinner: - Support for R8 chipset (used on NTC's $9 C.H.I.P board) Mediatek: - SMP support for some platforms Uniphier: - L2 support - Cleaned up SMP support, etc. plus a handful of other patches around above functionality, and a few other smaller changes" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits) ARM: uniphier: rework SMP operations to use trampoline code ARM: uniphier: add outer cache support Documentation: EXYNOS: Update bootloader interface on exynos542x ARM: mvebu: add broken-idle option ARM: orion5x: use mac_pton() helper ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned ARM: sunxi: Add R8 support ARM: digicolor: select pinctrl/gpio driver arm: berlin: add CPU hotplug support arm: berlin: use non-self-cleared reset register to reset cpu ARM: mediatek: add smp bringup code ARM: mediatek: enable gpt6 on boot up to make arch timer working soc: mediatek: Fix random hang up issue while kernel init soc: ti: qmss: make acc queue support optional in the driver soc: ti: add firmware file name as part of the driver Documentation: dt: soc: Add description for knav qmss driver ARM: S3C64XX: Use PWM lookup table for mach-smartq ARM: S3C64XX: Use PWM lookup table for mach-hmt ARM: S3C64XX: Use PWM lookup table for mach-crag6410 ARM: S3C64XX: Use PWM lookup table for smdk6410 ...
| * ARM: sunxi: Add R8 supportMaxime Ripard2015-10-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R8 is a new Allwinner SoC based on the A13. While both are very similar, there's still a few differences. Introduce a new compatible to deal with them. In order to have a consistent naming, instead of mentioning the Allwinner A series as the machine name, switch to sun4i/sun5i like what is done for the other families. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* | clocksource: cosmetic: Drop OF 'dependency' from symbolsMarc Zyngier2015-10-011-1/+1
|/ | | | | | | | | | | | | Seeing the 'of' characters in a symbol that is being called from ACPI seems to freak out people. So let's do a bit of pointless renaming so that these folks do feel at home. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* Merge tag 'sunxi-late-for-4.2' of ↵Kevin Hilman2015-07-102-2/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes Merge "Allwinner late changes for 4.2" from Maxime Ripard: Allwinner late changes for 4.2 A bunch of defconfig changes, and some patches to make the Allwinner H3 and A33 boot properly. * tag 'sunxi-late-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: sunxi: Enable simplefb in the defconfig ARM: Remove deprecated symbol from defconfig files ARM: sunxi: Add Machine support for A33 ARM: sunxi: Introduce Allwinner H3 support Documentation: sunxi: Update Allwinner SoC documentation
| * ARM: sunxi: Add Machine support for A33Vishnu Patekar2015-07-051-0/+1
| | | | | | | | | | | | | | | | | | | | Add machine support for the Allwinner A33 quad core cortex-a7 based SoC, which is similar to the A23 SoC. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Chen-Yu Tsai <wens@csie.org>
| * ARM: sunxi: Introduce Allwinner H3 supportJens Kuske2015-07-052-2/+4
| | | | | | | | | | | | | | | | The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar to other sun8i family SoCs like the A23. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sun8i: Add SMP support for the Allwinner A23Chen-Yu Tsai2015-04-271-0/+69
|/ | | | | | | | | The A23 is a dual Cortex-A7. Add the logic to use the IPs used to control the CPU configuration and the CPU power so that we can bring up secondary CPUs at boot. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usageChen-Yu Tsai2015-02-231-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | As the sunxi usb clocks all contain a reset controller, it is not possible to build the sunxi clock driver without RESET_CONTROLLER enabled. Doing so results in an undefined symbol error: drivers/built-in.o: In function `sunxi_gates_clk_setup': linux/drivers/clk/sunxi/clk-sunxi.c:1071: undefined reference to `reset_controller_register' This is possible if building a minimal kernel without PHY_SUN4I_USB. The dependency issue is made visible at compile time instead of link time by the new A80 mmc clocks, which also use a reset control itself. This patch makes ARCH_SUNXI select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER. Fixes: 559482d1f950 ARM: sunxi: Split the various SoCs support in Kconfig Cc: <stable@vger.kernel.org> # 3.16+ Reported-by: Lourens Rozema <ik@lourensrozema.nl> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: Register cpufreq-dt for sun[45678]iChen-Yu Tsai2015-01-071-0/+10
| | | | | | | | | On sun[45678]i, we have one cluster of identical cores sharing a clock, which is ideal for using cpufreq-dt. Register a platform device for cpufreq-dt. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxiHans de Goede2015-01-052-1/+2
| | | | | | | | | | So far the A31s is 100% compatible with the A31, still lets do the same as what we've done for the A13 / A10s and give it its own compatible string, in case we need to differentiate later. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [Maxime: Removed unusude CPU_OF_DECLARE_METHOD] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: make sun6i SMP ops staticEmilio López2014-11-161-1/+1
| | | | | | | | The sun6i SMP ops are currently not marked as static, as reported by sparse. Let's mark it as such. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER for sun9iChen-Yu Tsai2014-10-201-0/+2
| | | | | | | The A80 SoC has reset controls matching bus clock gates. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: Introduce Allwinner A80 supportChen-Yu Tsai2014-10-202-0/+14
| | | | | | | | | | The Allwinner A80 is a new Cortex octo-core A7/A15 big.LITTLE SoC. While it's processor cores and interconnecting bus are new, it re-uses many peripherals found in earlier Allwinner SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Andreas Färber <afaerber@suse.de>
* ARM: sunxi: Remove sun4i reboot code from mach directoryMaxime Ripard2014-09-111-76/+0
| | | | | | | | | | Now that the restart code has been merged in the watchdog driver, we don't need the restart code in the mach-sunxi directory anymore. Remove it entirely. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'soc-for-3.17' of ↵Linus Torvalds2014-08-082-0/+17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This is the bulk of new SoC enablement and other platform changes for 3.17: - Samsung S5PV210 has been converted to DT and multiplatform - Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms - Kirkwood, one of the popular Marvell platforms, is folded into the mvebu platform code, removing mach-kirkwood - Hwmod data for TI AM43xx and DRA7 platforms - More additions of Renesas shmobile platform support - Removal of plat-samsung contents that can be removed with S5PV210 being multiplatform/DT-enabled and the other two old platforms being removed New platforms (most with only basic support right now): - Hisilicon X5HD2 settop box chipset is introduced - Mediatek MT6589 (mobile chipset) is introduced - Broadcom BCM7xxx settop box chipset is introduced + as usual a lot other pieces all over the platform code" * tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits) ARM: hisi: remove smp from machine descriptor power: reset: move hisilicon reboot code ARM: dts: Add hix5hd2-dkb dts file. ARM: debug: Rename Hi3716 to HIX5HD2 ARM: hisi: enable hix5hd2 SoC ARM: hisi: add ARCH_HISI MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Documentation: arm: misc updates to Marvell EBU SoC status Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC ARM: mvebu: fix build without platforms selected ARM: mvebu: add cpuidle support for Armada 38x ARM: mvebu: add cpuidle support for Armada 370 cpuidle: mvebu: add Armada 38x support cpuidle: mvebu: add Armada 370 support cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 ARM: mvebu: export the SCU address ...
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 10:21:49 +0100