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path: root/arch/arm/mm/cache-l2x0.c (follow)
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* ARM: 8890/1: l2x0: add marvell,ecc-enable property for auroraChris Packham2019-08-291-0/+5
* ARM: 8886/1: l2x0: support parity-enable/disable on auroraChris Packham2019-08-291-0/+7
* ARM: 8887/1: aurora-l2: add prefix to MAX_RANGE_SIZEJan Luebbe2019-08-291-2/+2
* ARM: 8902/1: l2c: move cache-aurora-l2.h to asm/hardwareJan Luebbe2019-08-291-1/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333Thomas Gleixner2019-06-051-13/+1
* ARM: 8659/1: l2c: allow CA9 optimizations to be disabledChris Brandt2017-03-171-2/+11
* cpu/hotplug: Cleanup state namesThomas Gleixner2016-12-251-1/+1
* ARM: 8611/1: l2x0: add PMU supportMark Rutland2016-09-061-0/+6
* ARM: 8593/1: cache-l2x0.c: Do not clear bit 23 in prefetch control registerAndrey Smirnov2016-08-121-5/+2
* ARM: 8592/1: cache-l2x0.c: Replace magic numbersAndrey Smirnov2016-08-121-2/+4
* arm/l2c: Convert to hotplug state machineRichard Cochran2016-07-151-14/+13
* ARM: 8569/1: pl2x0: Add OF control of cache power managementBrad Mouring2016-05-051-5/+21
* ARM: 8482/1: l2x0: make it possible to disable outer sync from DTLinus Walleij2015-12-221-3/+10
* ARM: 8448/1: add some L220 DT settingsLinus Walleij2015-11-161-0/+20
* ARM: 8395/1: l2c: Add support for the "arm,shared-override" propertyGeert Uytterhoeven2015-07-101-0/+5
* ARM: 8391/1: l2c: add options to overwrite prefetching behaviorHauke Mehrtens2015-06-111-0/+20
* ARM: l2c: avoid passing auxiliary control register through enable methodRussell King2015-05-151-15/+17
* ARM: l2c: only unlock caches if NS_LOCKDOWN bit is setRussell King2015-05-151-1/+25
* ARM: l2c: clean up l2c_configure()Russell King2015-05-151-9/+14
* ARM: l2c: write auxiliary control register firstRussell King2015-05-151-2/+2
* ARM: l2c: restore the behaviour documented above l2c_enable()Russell King2015-05-151-5/+5
*-. Merge branches 'misc', 'vdso' and 'fixes' into for-nextRussell King2015-04-141-17/+16
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| | * ARM: 8310/1: l2c: Fix prefetch settings dt parsingFabrice Gasnier2015-03-181-17/+16
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* / ARM: 8309/1: l2c: enforce use of cache-level propertyFlorian Fainelli2015-03-101-0/+7
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* Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds2015-02-121-209/+230
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| * ARM: 8297/1: cache-l2x0: optimize aurora range operationsArnd Bergmann2015-02-061-46/+22
| * ARM: 8296/1: cache-l2x0: clean up aurora cache handlingArnd Bergmann2015-02-061-73/+38
| * ARM: 8262/1: l2c: Add support for overriding prefetch settingsTomasz Figa2015-01-161-0/+54
| * ARM: 8260/1: l2c: Add interface to ask hypervisor to configure L2CTomasz Figa2015-01-161-0/+6
| * ARM: 8259/1: l2c: Refactor the driver to use commit-like interfaceTomasz Figa2015-01-161-96/+116
| * ARM: 8258/1: l2c: use l2c_write_sec() for restoring latency and filter regsMarek Szyprowski2015-01-161-16/+16
* | ARM: cache-l2x0.c: Make it clear that cache-l2x0 handles L310 cache controllerPavel Machek2015-01-201-1/+1
* | ARM: l2c: fix commentGeert Uytterhoeven2015-01-201-1/+1
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* ARM: 8183/1: l2c: Improve l2c310_of_parse() error messageFabio Estevam2014-10-291-2/+2
* ARM: 8182/1: l2c: Make l2x0_cache_size_of_parse() return 'int'Fabio Estevam2014-10-291-6/+16
* ARM: 8169/1: l2c: parse cache properties from ePAPR definitionsLinus Walleij2014-10-021-0/+121
* Merge branches 'fixes' and 'misc' into for-nextRussell King2014-08-051-1/+1
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| * ARM: make it easier to check the CPU part number correctlyRussell King2014-07-181-1/+1
* | ARM: l2c: fix revision checkingRussell King2014-07-071-1/+1
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* ARM: 8076/1: mm: add support for HW coherent systems in PL310 cacheThomas Petazzoni2014-06-291-0/+31
* ARM: l2c: trial at enabling some Cortex-A9 optimisationsRussell King2014-05-301-3/+70
* ARM: l2c: add warnings for stuff modifying aux_ctrl register valuesRussell King2014-05-301-3/+22
* ARM: l2c: print a warning with L2C-310 caches if the cache size is modifiedRussell King2014-05-301-0/+2
* ARM: l2c: remove old .set_debug methodRussell King2014-05-301-19/+2
* ARM: l2c: always enable non-secure access to lockdown registersRussell King2014-05-301-2/+21
* ARM: l2c: always enable low power modesRussell King2014-05-301-0/+12
* ARM: l2c: add automatic enable of early BRESPRussell King2014-05-301-3/+22
* ARM: l2c: move L2 cache register saving to a more sensible locationRussell King2014-05-301-12/+22
* ARM: l2c: check that DT files specify the required "cache-unified" propertyRussell King2014-05-301-0/+4
* ARM: l2c: fix register namingRussell King2014-05-301-28/+29
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