linux - linux

	Commit message (Collapse)	Author	Age	Files	Lines
*	ARM: l2c: tauros2: use descriptive definitions for register bits	Russell King	2015-11-26	1	-5/+10
\| \| \| \| \| \| \|	Use descriptive definitions for the Tauros2 register bits, and while we're here, clean up the "Tauros2: %s line fill burt8." message. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
*	ARM: l2c: tauros2: fix OF-enabled non-DT boot	Russell King	2015-11-26	1	-9/+8
\| \| \| \|	Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
*	ARM: convert printk(KERN_* to pr_*	Russell King	2014-11-21	1	-6/+6
\| \| \| \| \| \| \| \| \| \| \|	Convert many (but not all) printk(KERN_* to pr_* to simplify the code. We take the opportunity to join some printk lines together so we don't split the message across several lines, and we also add a few levels to some messages which were previously missing them. Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
*	ARM: cache-tauros2: remove ARMv6 code	Arnd Bergmann	2014-03-27	1	-28/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode. Removing the ARMv6 code path reduces the code size and avoids the linker error. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
*	ARM: cache: add dt support for tauros2 cache	Chao Xie	2012-08-16	1	-1/+34
\| \| \| \| \|	Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
*	ARM: cache: add extra feature enable for tauros2	Chao Xie	2012-08-16	1	-17/+27
\| \| \| \| \| \| \| \|	The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
*	ARM: cache: add cputype.h for tauros2	Chao Xie	2012-08-16	1	-3/+1
\| \| \| \| \|	Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
*	ARM: cache: fix uninitialized ptr in tauros2_init	Chao Xie	2012-08-16	1	-1/+1
\| \| \| \| \| \| \| \|	init the variable "mode" to NULL to ensure the later NULL checking is taking effect. Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
*	ARM: cache: tauros2: add disable and resume callback	Chao Xie	2012-05-07	1	-0/+24
\| \| \| \| \| \| \| \|	For the SOC chips using tauros2 cache, will need disable and resume tauros2 cache for SOC suspend/resume. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
*	ARM: move CP15 definitions to separate header file	Russell King	2012-03-28	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Avoid namespace conflicts with drivers over the CP15 definitions by moving CP15 related prototypes and definitions to a private header file. Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> [Tegra] Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> [EP93xx] Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: David Howells <dhowells@redhat.com>
*	ARM: Add Tauros2 L2 cache controller support	Lennert Buytenhek	2009-11-27	1	-0/+263
	Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>