summaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/cache-v6.S (follow)
Commit message (Collapse)AuthorAgeFilesLines
* ARM: 6111/1: Implement read/write for ownership in the ARMv6 DMA cache opsCatalin Marinas2010-05-081-4/+13
| | | | | | | | | | | | | | The Snoop Control Unit on the ARM11MPCore hardware does not detect the cache operations and the dma_cache_maint*() functions may leave stale cache entries on other CPUs. The solution implemented in this patch performs a Read or Write For Ownership in the ARMv6 DMA cache maintenance functions. These LDR/STR instructions change the cache line state to shared or exclusive so that the cache maintenance operation has the desired effect. Tested-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: dma-mapping: fix for speculative prefetchingRussell King2010-02-151-4/+6
| | | | | | | | | | | | | | | | | ARMv6 and ARMv7 CPUs can perform speculative prefetching, which makes DMA cache coherency handling slightly more interesting. Rather than being able to rely upon the CPU not accessing the DMA buffer until DMA has completed, we now must expect that the cache could be loaded with possibly stale data from the DMA buffer. Where DMA involves data being transferred to the device, we clean the cache before handing it over for DMA, otherwise we invalidate the buffer to get rid of potential writebacks. On DMA Completion, if data was transferred from the device, we invalidate the buffer to get rid of any stale speculative prefetches. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: dma-mapping: remove dmac_clean_range and dmac_inv_rangeRussell King2010-02-151-4/+2
| | | | | | | These are now unused, and so can be removed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: dma-mapping: provide per-cpu type map/unmap functionsRussell King2010-02-151-0/+26
| | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: add size argument to __cpuc_flush_dcache_pageRussell King2009-12-141-5/+6
| | | | | | | ... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5746/1: Handle possible translation errors in ARMv6/v7 coherent_user_rangeCatalin Marinas2009-10-071-2/+18
| | | | | | | | | | This is needed because applications using the sys_cacheflush system call can pass a memory range which isn't mapped yet even though the corresponding vma is valid. The patch also adds unwinding annotations for correct backtraces from the coherent_user_range() functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation ↵Catalin Marinas2009-04-301-0/+33
| | | | | | | | | | can fail This patch implements the recommended workaround for erratum 411920 (ARM1136, ARM1156, ARM1176). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problemCatalin Marinas2006-03-101-3/+4
| | | | | | | | | | | | | | | | Patch from Catalin Marinas ARM1136 erratum 371025 (category 2) specifies that, under rare conditions, an invalidate I-cache by MVA (line or range) operation can fail to invalidate a cache line. The recommended workaround is to either invalidate the entire I-cache or invalidate the range by set/way rather than MVA. Note that for a 16K cache size, invalidating a 4K page by set/way is equivalent to invalidating the entire I-cache. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3294/1: don't invalidate individual BTB entries on ARMv6Nicolas Pitre2006-02-011-12/+6
| | | | | | | | | | Patch from Nicolas Pitre Doing so adds a much larger cost to the loop than the cost implied by simply invalidating the whole BTB at once. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.SGen FUKATSU2005-09-301-1/+8
| | | | | | | | | | | | Patch from Gen FUKATSU Invalidate BTB entry instruction flushes two instruction at a time. Therefore this instruction should be done four times after invalidate instruction cache line. Signed-off-by: Gen Fukatsu Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-171-0/+227
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 20:57:50 +0100