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context.c
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Author
Age
Files
Lines
*
ARM: mm: make vmalloc_seq handling SMP safe
Ard Biesheuvel
2022-01-25
1
-2
/
+1
*
ARM: 9150/1: Fix PID_IN_CONTEXTIDR regression when THREAD_INFO_IN_TASK=y
Ard Biesheuvel
2021-10-30
1
-1
/
+1
*
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
Thomas Gleixner
2019-06-19
1
-4
/
+1
*
ARM: 8465/1: mm: keep reserved ASIDs in sync with mm after multiple rollovers
Will Deacon
2015-12-03
1
-12
/
+26
*
ARM: 8299/1: mm: ensure local active ASID is marked as allocated on rollover
Will Deacon
2015-02-03
1
-15
/
+11
*
ARM: 8203/1: mm: try to re-use old ASID assignments following a rollover
Will Deacon
2014-11-21
1
-24
/
+34
*
ARM: 7926/1: mm: flesh out and fix the comments in the ASID allocator
Will Deacon
2013-12-29
1
-6
/
+10
*
ARM: 7925/1: mm: keep track of last ASID allocation to improve bitmap searching
Will Deacon
2013-12-29
1
-1
/
+3
*
ARM: 7924/1: mm: don't bother with reserved ttbr0 when running with LPAE
Will Deacon
2013-12-29
1
-10
/
+11
*
ARM: tlb: don't perform inner-shareable invalidation for local TLB ops
Will Deacon
2013-08-12
1
-6
/
+1
*
ARM: 7789/1: Do not run dummy_flush_tlb_a15_erratum() on non-Cortex-A15
Fabio Estevam
2013-07-26
1
-1
/
+2
*
Merge branch 'devel-stable' into for-next
Russell King
2013-06-29
1
-7
/
+2
|
\
|
*
ARM: LPAE: use 64-bit accessors for TTBR registers
Cyril Chemparathy
2013-05-30
1
-7
/
+2
*
|
ARM: 7769/1: Cortex-A15: fix erratum 798181 implementation
Marc Zyngier
2013-06-24
1
-1
/
+28
*
|
ARM: 7768/1: prevent risks of out-of-bound access in ASID allocator
Marc Zyngier
2013-06-24
1
-9
/
+8
*
|
ARM: 7767/1: let the ASID allocator handle suspended animation
Marc Zyngier
2013-06-24
1
-0
/
+9
|
/
*
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB opera...
Catalin Marinas
2013-04-03
1
-1
/
+2
*
ARM: 7661/1: mm: perform explicit branch predictor maintenance when required
Will Deacon
2013-03-03
1
-1
/
+3
*
ARM: 7659/1: mm: make mm->context.id an atomic64_t variable
Will Deacon
2013-03-03
1
-8
/
+13
*
ARM: 7658/1: mm: fix race updating mm->context.id on ASID rollover
Will Deacon
2013-03-03
1
-3
/
+3
*
ARM: 7649/1: mm: mm->context.id fix for big-endian
Ben Dooks
2013-02-16
1
-0
/
+3
*
ARM: 7582/2: rename kvm_seq to vmalloc_seq so to avoid confusion with KVM
Nicolas Pitre
2012-11-26
1
-2
/
+2
*
ARM: mm: use bitmap operations when allocating new ASIDs
Will Deacon
2012-11-05
1
-19
/
+35
*
ARM: mm: avoid taking ASID spinlock on fastpath
Will Deacon
2012-11-05
1
-8
/
+15
*
ARM: mm: remove IPI broadcasting on ASID rollover
Will Deacon
2012-11-05
1
-100
/
+86
*
ARM: 7502/1: contextidr: avoid using bfi instruction during notifier
Will Deacon
2012-08-25
1
-3
/
+4
*
ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process
Will Deacon
2012-07-09
1
-0
/
+35
*
ARM: Remove current_mm per-cpu variable
Catalin Marinas
2012-04-17
1
-11
/
+1
*
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs
Catalin Marinas
2012-04-17
1
-2
/
+2
*
ARM: Use TTBR1 instead of reserved context ID
Will Deacon
2012-04-17
1
-18
/
+27
*
ARM: LPAE: Add context switching support
Catalin Marinas
2011-12-08
1
-2
/
+17
*
locking, ARM: Annotate low level hw locks as raw
Thomas Gleixner
2011-09-13
1
-7
/
+7
*
Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks"
Russell King
2011-06-09
1
-3
/
+3
*
Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"
Russell King
2011-06-09
1
-6
/
+5
*
ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks
Will Deacon
2011-05-26
1
-3
/
+3
*
ARM: 6943/1: mm: use TTBR1 instead of reserved context ID
Will Deacon
2011-05-26
1
-5
/
+6
*
ARM: 5905/1: ARM: Global ASID allocation on SMP
Catalin Marinas
2010-02-15
1
-14
/
+110
*
ARM: Fix errata 411920 workarounds
Russell King
2009-10-29
1
-4
/
+1
*
cpumask: use mm_cpumask() wrapper: arm
Rusty Russell
2009-09-24
1
-1
/
+1
*
-
.
Merge branches 'armv7', 'at91', 'misc' and 'omap' into devel
Russell King
2007-05-09
1
-3
/
+7
|
\
\
|
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*
[ARM] Fix ASID version switch
Russell King
2007-05-08
1
-3
/
+7
|
|
/
*
/
[ARM] armv7: add support for asid-tagged VIVT I-cache
Catalin Marinas
2007-05-09
1
-0
/
+7
|
/
*
[ARM] 4128/1: Architecture compliant TTBR changing sequence
Catalin Marinas
2007-02-08
1
-2
/
+10
*
[ARM] Move mmu.c out of the way
Russell King
2006-09-20
1
-0
/
+45