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path: root/arch/arm/mm/proc-v7.S (follow)
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* ARM: 6435/1: Fix HWCAP_TLS flag for ARM11MPCore/Cortex-A9Tony Lindgren2010-10-081-1/+1
* ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to d...Will Deacon2010-10-041-0/+8
* ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARMDaniel Walker2010-09-171-1/+25
* ARM: 6389/1: errata: incorrect hazard handling in the SCU may lead to data co...Will Deacon2010-09-171-0/+9
* ARM: 6388/1: errata: DMB operation may be faultyWill Deacon2010-09-171-2/+14
* ARM: 6387/1: errata: check primary part ID in proc-v7.SWill Deacon2010-09-171-3/+8
* ARM: Factor out common code from cpu_proc_fin()Russell King2010-07-271-4/+1
* ARM: 6207/1: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6Tony Lindgren2010-07-091-1/+1
* ARM: 5888/1: arm: Update comments in cacheflush.h and remove unnecessary V6 a...Tony Lindgren2010-01-201-2/+0
* ARM: 5886/1: arm: Fix cpu_proc_fin() for proc-v7.S and make kexec workTony Lindgren2010-01-191-1/+8
* ARMv7: Check whether the SMP/nAMP mode was already enabledTony Thompson2009-11-041-3/+4
* ARM: ensure initial page tables are setup for SMP systemsRussell King2009-11-021-3/+4
* ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()Kirill A. Shutemov2009-10-021-1/+1
* nommu: Do not set PRRR and NMRR in proc-v7.S if !MMUCatalin Marinas2009-07-241-1/+1
* Thumb-2: Implement the unified arch/arm/mm supportCatalin Marinas2009-07-241-1/+4
* Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2009-06-141-11/+48
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| * Add core support for ARMv6/v7 big-endianCatalin Marinas2009-05-301-0/+3
| * ARMv7: Document the PRRR and NMRR registers settingCatalin Marinas2009-05-301-2/+30
| * ARMv7: Enable the SWP instructionCatalin Marinas2009-05-301-4/+4
| * ARMv7: Mark the PTWs inner WBWA on SMP and WB on UPTony Thompson2009-05-301-3/+9
| * Check whether the TLB operations need broadcasting on SMP systemsCatalin Marinas2009-05-301-2/+2
* | [ARM] ARMv7 errata: only apply fixes when running on applicable CPURussell King2009-06-021-11/+25
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* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2009-05-031-0/+19
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| * [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten wit...Catalin Marinas2009-04-301-0/+5
| * [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is createdCatalin Marinas2009-04-301-0/+6
| * [ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branchCatalin Marinas2009-04-301-0/+8
* | arm: Use __INIT macro instead of .text.init.Tim Abbott2009-04-281-1/+2
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* Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into develRussell King2008-11-271-3/+16
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| * Modern processors may need to drain the WB before WFICatalin Marinas2008-11-101-0/+1
| * ARMv7: Add SMP initialisation to proc-v7.SJon Callan2008-11-061-2/+15
| * ARMv7: Do not set TTBR0 in __v7_setupCatalin Marinas2008-11-061-1/+0
* | [ARM] mm: fix page table initializationRussell King2008-11-061-6/+6
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* [ARM] 5318/1: Swap the PRRR and NMRR values in proc-v7.SCatalin Marinas2008-10-221-2/+2
* Merge branch 'ptebits' into develRussell King2008-10-091-17/+12
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| * [ARM] Don't include asm/elf.h in asm codeRussell King2008-10-011-1/+1
| * [ARM] Convert ARMv7 to use TEX remappingRussell King2008-10-011-4/+33
| * [ARM] Convert ARMv6 and ARMv7 to use new memory typesRussell King2008-10-011-1/+3
| * [ARM] Convert set_pte_ext implementions to macrosRussell King2008-10-011-37/+1
* | [ARM] 5229/3: Replace some ARMv7 opcodes with the instruction nameCatalin Marinas2008-10-031-1/+1
* | [ARM] 5227/1: Add the ENDPROC declarations to the .S filesCatalin Marinas2008-09-011-0/+8
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* [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84fCatalin Marinas2008-04-241-1/+1
* Add a prefetch abort handlerPaul Brook2008-04-181-0/+1
* [ARM] 4503/1: nommu: Add noMMU support for ARMv7Catalin Marinas2007-07-201-11/+14
* [ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl registerCatalin Marinas2007-07-201-10/+0
* [ARM] 4394/1: ARMv7: Add the TLB range operationsCatalin Marinas2007-05-301-1/+1
* [ARM] armv7: add support for ARMv7 cores.Catalin Marinas2007-05-081-0/+262